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CXD3017Q Datasheet(PDF) 33 Page - Sony Corporation |
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CXD3017Q Datasheet(HTML) 33 Page - Sony Corporation |
33 / 117 page – 33 – CXD3017Q Command bit VCOSEL1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Multiplier PLL VCO1 is set to 1 × speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to 1 × speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to 1 × speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to 1 × speed, and the output is 1/8 frequency-divided. Multiplier PLL VCO1 is set to about 2 × speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to about 2 × speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to about 2 × speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to about 2 × speed, and the output is 1/8 frequency-divided. KSL3 KSL2 Processing Command bit VCO1CS0 = 0 Processing Multiplier PLL VCO1 low speed is selected. Multiplier PLL VCO1 high speed is selected. ∗ The CXD3017Q has two VCO1s, and this command selects one of these VCO1s. VCO1CS0 = 1 1/2 1/1 1/8 1/4 To DSP interior KSL3, 2 VCO1CS0 Low-speed VCO1 High-speed VCO1 VCO1SEL1 ∗ Block Diagram of VCO Internal Path VCO1 Internal Path Command bit TXON = 0 Processing When CD TEXT data in not demodulated, set TXON to 0. When CD TEXT data in demodulated, set TXON to 1. ∗ See "$3-13. CD TEXT Data Demodulation" TXON = 1 |
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