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CXD2724AQ-3 Datasheet(PDF) 7 Page - Sony Corporation

Part No. CXD2724AQ-3
Description  Single-Chip Dolby Pro Logic Surround Decoder
Download  65 Pages
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD2724AQ-3 Datasheet(HTML) 7 Page - Sony Corporation

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CXD2724AQ-3
Microcomputer Interface Timing
Transfer timing for address section, transfer mode section and data section LSB
Transfer timing from data section MSB to address section and transfer mode section
Notes) 1. t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs)
2. The REDY pin is the value for CL = 60pF.
Item
RVDT data setup time relative to SCK rise
RVDT data hold time from SCK rise
SCK Low level width
SCK High level width
XLAT Low level width
XLAT High level width
SCK rise preceding time relative to XLAT rise
SCK rise wait time relative to XLAT rise
Delay time to REDY fall relative to SCK rise
REDY fall preceding time relative to SCK rise
REDY rise preceding time relative to XLAT rise
REDY rise preceding time relative to SCK fall
XLAT fall wait time relative to SCK rise
XLAT fall delay time relative to REDY fall
SCK rise wait time for next transfer
Symbol
tDS
tDH
tSWL
tSWH
tLWL
tLWH
tSLP
tLSD
tSBD
tBSP
tRLP
tRSDP
tSLD
tLDR
tSS
Min.
20
1t + 20
1t + 20
1t + 20
1t + 20
1t + 20
20
3t + 20
20
20
20
3t + 20
20
2t + 40
Max.
4t + 50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RVDT
SCK
tSWL
tSWH
tDS
tDH
Address LSB
Mode MSB
0.3VDD
0.7VDD
0.3VDD
0.7VDD
tSLP
tLSD
tLWL
0.3VDD
0.7VDD
XLAT
REDY
Data LSB
Data MSB
RVDT
SCK
XLAT
REDY
Mode MSB
0.3VDD
0.7VDD
Address LSB
Data MSB
tSS
tLDR
tSBD
tSLD
tBSP
0.3VDD
0.7VDD
tRLP
0.3VDD
0.7VDD


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