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CXD2724AQ-1 Datasheet(PDF) 60 Page - Sony Corporation

Part No. CXD2724AQ-1
Description  Single-Chip Dolby Pro Logic Surround Decoder
Download  65 Pages
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD2724AQ-1 Datasheet(HTML) 60 Page - Sony Corporation

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CXD2724AQ-1
0000H
36.0ms
6340H
6360H
tp_fb
ap0_in
69.6ms (0000H to bfe0H)
9180H
ap0_out
91a0H
ap1_in
bfe0H
ap1_out
16.8ms
16.8ms
Fig. 8-5-3. Delay Time Setting Example (1/2 Decimation)
Note) Assuming the tap read address to be 0000H, the comb filter has a delay time of "0". However, the all
pass filters are delayed by one sample after reading from the delay RAM.
Therefore, perfect through operation is not possible even if (write address) = (read address).
Table 8-5-12. SFC Mode Delay Time Setting Value Examples
(7)-2. All Pass Filters (APF0, APF1)
The all pass filter delay times are determined by (read address) – (write address - 0020H). Set ap∗_in and
ap∗_out so that this subtraction results in the target delay time setting value. The calculation method is the
same as that for tp_fb.
Example) When setting a maximum comb filter delay time of 36ms and splitting the remainder evenly
between APF0 and APF1.
(1/2 decimation)
(bfe0H – 6340H)/2 = 2e50H
The address is specified in 0020H increments, so 2e40H is used for APF0, and 2e60H for APF1.
tp_fb = 6340H, so:
ap0_in = 6360H, ap0_out = 6340H + 2e40H = 9180H
ap1_in = 91a0H, ap1_out = 9180H + 2e60H = bfe0H
0020H
0040H
·
·
3720H
·
6e40H
·
a560H
·
bf80H
bfa0H
0.022ms
0.045ms
·
·
10.000ms
·
20.000ms
·
30.000ms
·
34.739ms
34.761ms
0.045ms
0.090ms
·
·
20.000ms
·
40.000ms
·
60.000ms
·
69.478ms
69.523ms
0.068ms
0.136ms
·
·
30.000ms
·
60.000ms
·
90.000ms
·
104.217ms
104.285ms
Setting
value
Delay (fs = 44.1kHz)
1/1 (No decimation)
1/2 decimation
1/3 decimation


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