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CXD2720Q-2 Datasheet(PDF) 19 Page - Sony Corporation

Part No. CXD2720Q-2
Description  Single-Chip Dolby Pro Logic Surround Decoder
Download  47 Pages
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD2720Q-2 Datasheet(HTML) 19 Page - Sony Corporation

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CXD2720Q-2
(2) Description of Communication Formats
The data transmission timing between the microcomputer interface and coefficient RAM and setup register is
called the SV cycle, and is generated once in 1LRCK.
The SV cycle is generated immediately preceding the signal processing program, so it has absolutely no effect
on signal processing, and there is no risk of the sound being cut.
In read/write modes,
Address section + Mode section + Data section
act as one package of data to perform data transmission between the microcomputer and the CXD2720Q-2.
[Write] • For coefficient RAM
Address section (8 bits)
Mode section (8 bits)
Data section (16 bits)
A0
A7
M0
M7
D0
D15
RVDT
SCK
XLAT
REDY
TRDT
[Read] • For coefficient RAM
Address section (8 bits) Mode section (8 bits)
Data section (16 bits)
A0
A7
M0
M7
D0
D15
RVDT
SCK
XLAT
REDY
TRDT
Note) For both read and write, the data section is 24 bits for the setup register.
Figure 6-1. Examples of Communication


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