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IS49NLS93200 Datasheet(PDF) 3 Page - Integrated Silicon Solution, Inc |
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IS49NLS93200 Datasheet(HTML) 3 Page - Integrated Silicon Solution, Inc |
3 / 34 page IS49NLS93200,IS49NLS18160 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00F, 09/25/2012 3 1.2 288Mb (16Mx18) Separate I/O BGA Ball-out (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A VREF VSS VEXT VSS VSS VEXT TMS TCK B VDD D4 Q4 VSSQ VSSQ Q0 D0 VDD C VTT D5 Q5 VDDQ VDDQ Q1 D1 VTT D A221 D6 Q6 VSSQ VSSQ QK0# QK0 VSS E A212 D7 Q7 VDDQ VDDQ Q2 D2 A202 F A5 D8 Q8 VSSQ VSSQ Q3 D3 QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H BA2 A9 VSS VSS VSS VSS A4 A3 J NF3 NF3 VDD VDD VDD VDD BA0 CK K DK DK# VDD VDD VDD VDD BA1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 N A18 D14 Q14 VSSQ VSSQ Q9 D9 A19 P A15 D15 Q15 VDDQ VDDQ Q10 D10 DM R VSS QK1 QK1# VSSQ VSSQ Q11 D11 VSS T VTT D16 Q16 VDDQ VDDQ Q12 D12 VTT U VDD D17 Q17 VSSQ VSSQ Q13 D13 VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Symbol Description Ball count VDD Supply voltage 16 VSS Ground 16 VDDQ DQ power supply 8 VSSQ DQ Ground 12 VEXT Supply voltage 4 VREF Reference voltage 2 VTT Termination voltage 4 A* Address - A0-22 23 BA* Banks - BA0-2 3 D* Input data 18 Q* Output data 18 DK* Input data clock(Differential inputs) 2 QK* Output data clocks(outputs) 4 CK* Input clocks (CK, CK#) 2 DM Input data mask 1 CS#,WE#,REF# Command control pins 3 ZQ External impedance (25–60Ω) 1 QVLD Data valid 1 NF Do not use, No function 2 T* JTAG - TCK,TMS,TDO,TDI 4 Total 144 NOTES: 1) Reserved for future use. This may optionally be connected to GND. 2) Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND. 3) No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND. 4) Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins will be connected to VTT. NOTES: 1) Reserved for future use. This may optionally be connected to GND. 2) Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND. 3) No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND. 4) Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins will be connected to VTT. Notes: 1. Reserved for future use. This may optionally be connected to GND. 2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND. 3. No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND. |
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