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LMK212BJ226MG-T Datasheet(PDF) 3 Page - Enpirion, Inc. |
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LMK212BJ226MG-T Datasheet(HTML) 3 Page - Enpirion, Inc. |
3 / 21 page EN2390QI © Enpirion 2012 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 3 Pin Description I/O Legend: P=Power G=Ground NC=No Connect I=Input O=Output I/O=Input/Output PIN NAME I/O FUNCTION 1-19, 29, 30, 61, 67, 72-76 NC NC NO CONNECT – These pins may be internally connected. Do not connect them to each other or to any other electrical signal. Failure to follow this guideline may result in device damage. 20-28 VOUT O Regulated converter output. Connect these pins to the load and place output capacitor between these pins and PGND pins 33-38. 31, 32, 69-71 NC(SW) NC NO CONNECT – These pins are internally connected to the common switching node of the internal MOSFETs. They are not to be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in damage to the device. 33-38 PGND G Input/Output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT and PVIN pin descriptions for more details. 39-49 PVIN P Input power supply. Connect to input power supply. Decouple with input capacitor to PGND pins 33-38. 50 AVINO O Internal 3.3V linear regulator output. Connect this pin to AVIN (Pin 59) for applications where operation from a single input voltage (PVIN) is required. If AVINO is being used, place a 1uF, X5R, capacitor between AVINO and AGND as close as possible to AVINO. 51 PG I/O Place a 0.1uF, X5R, capacitor between this pin and BTMP. 52 BTMP I/O See pin 51 description. 53 VDDB O Internal regulated voltage used for the internal control circuitry. Place a 1uF, X5R, capacitor between this pin and BGND. 54 BGND G See pin 53 description. 55 S_IN I Digital Input. This pin accepts either an input clock to phase lock the internal switching frequency or a S_OUT signal from another EN2390QI. Leave this pin floating if not used. 56 S_OUT O Digital Output. PWM signal is output on this pin. Leave this pin floating if not used. 57 POK O Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power system state indication. POK is logic high when VOUT is within -10% to +20% of VOUT nominal. 58 ENABLE I Input Enable. Applying a logic high to this pin enables the output and initiates a soft-start. Applying a logic Low disables the output. 59 AVIN P 3.3V Input power supply for the controller. Place a 0.1uF, X5R, capacitor between AVIN and AGND 60 AGND G Analog Ground. This is the Ground return for the controller. Needs to be connected to a quiet ground. 61 NC Test pin. For Enpirion Internal Use Only. Connect to GND plane at all times. 62 VFB I/O External Feedback Input. The feedback loop is closed through this pin. A voltage divider at VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A phase lead capacitor from this pin to VOUT is also required to stabilize the loop. 63 EAIN O Optional Error Amplifier Input. Allows for customization of the control loop if necessary. 64 SS I/O Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value of this capacitor determines the startup time. 65 RCLX I/O Programmable over-current protection. Placement of a resistor on this pin will adjust the over-current protection threshold. See Table 2 for the recommended RCLX Value to set OCP at the nominal value specified in the Electrical Characteristics table. 66 FADJ I/O Adding a resistor (RFADJ) to this pin will adjust the switching frequency of the EN2390QI. See Table 1 for suggested resistor values on RFADJ for various PVIN/VOUT combinations to maximize efficiency. |
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