– 8 –

CXD2452R

(Within the recommended operating conditions)

Symbol

Output signal delay, activated by the rising edge of SEN

5

100

ns

Definition

Min.

Typ.

Max.

Unit

5) Phase identification characteristics using FRI and HRI input

FRI

HRI

tpd1

The field is identified as an ODD field .

FRI

HRI

tpd1

The field is identified as an EVEN field .

When the HRI logic level is low tpd1 after the

falling edge of FRI

When the HRI logic level is high tpd1 after the

falling edge of FRI

(Within the recommended operating conditions)

Symbol

Field identification clock phase, activated by the falling edge of FRI

1100

1300

ns

Definition

Min.

Typ.

Max.

Unit

4) RST loading characteristics

tw1

RST

(Within the recommended operating conditions)

Symbol

RST pulse width

35

ns

Definition

Min.

Typ.

Max.

Unit

3) Serial interface clock output variation characteristics

Normally, the serial interface data is loaded to the CXD2452R at the timing shown in 2) above. However, one

exception to this is when the data such as SSGSEL and STB is loaded to the CXD2452R and controlled at the

rising edge of SEN. For STB, see control data D62 to D63 STB in “Description of Operation”.

tpdPULSE

SEN

Output signal