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LMK212BJ226MG-T Datasheet(PDF) 5 Page - Enpirion, Inc. |
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LMK212BJ226MG-T Datasheet(HTML) 5 Page - Enpirion, Inc. |
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5 / 26 page  EN23F0QI ©Enpirion 2012 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 5 Electrical Characteristics NOTE: VIN=12V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at TA = 25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Operating Input Voltage PVIN 4.5 14.0 V Controller Input Voltage AVIN 2.5 5.5 V PVIN Under Voltage Lock-out UVLOPVIN Voltage above which UVLO is not asserted 2 V AVIN Under Voltage Lock-out rising AVINUVLOR Voltage above which UVLO is not asserted 2.3 V AVIN Under Voltage Lock-out falling AVINOVLOF Voltage below which UVLO is asserted 2.1 V AVIN Pin Input Current IAVIN 14 mA Internal Linear Regulator Output Voltage AVINO 3.3 V Shut-Down Supply Current IPVINS PVIN=12V, AVIN=3.3, ENABLE=0V 300 μA IAVINS PVIN=12V, AVIN=3.3, ENABLE=0V 50 μA Feedback Pin Voltage VFB Feedback Node Voltage at: VIN = 12V, ILOAD = 0, TA = 25°C 0.594 0.60 0.606 V Feedback Pin Voltage VFB Feedback Node Voltage at: 4.5V ≤ VIN ≤ 14V 0A ≤ ILOAD ≤ 15A, TA = -40 to 85°C 0.588 0.60 0.612 V Feedback pin Input Leakage Current IFB VFB pin input leakage current (Note 3) -5 5 nA VOUT Rise Time tRISE CSS = 47nF (Note 3, Note 4 and Note 5) 1.96 2.8 3.64 ms Soft Start Capacitor Range CSS_RANGE 47 nF Continuous Output Current IOUT_CONT 0 15 A Over Current Trip Level IOCP Reference Table 3 22.5 A ENABLE Logic High VENABLE_HIGH 4.5V ≤ VIN ≤ 14V; 1.8 AVIN V ENABLE Logic Low VENABLE_LOW 4.5V ≤ VIN ≤ 14V; 0 0.6 V ENABLE Lockout Time TENLOCKOUT 8 ms ENABLE pin Input Current IENABLE 180k Ω Pull Down (Note 3) 4 μA Switching Frequency FSW RFADJ =3kΩ 1.0 MHz External SYNC Clock Frequency Lock Range FPLL_LOCK Range of SYNC clock frequency 0.8 1.6 MHz S_IN Threshold – Low VS_IN_LO S_IN Clock Logic Low Level 0.8 V S_IN Threshold – High VS_IN_HI S_IN Clock Logic High Level 1.8 2.5 V S_OUT Threshold – Low VS_OUT_LO S_OUT Clock Logic Low Level 0.8 V S_OUT Threshold – High VS_OUT_HI S_OUT Clock Logic High Level 1.8 2.5 V POK Lower Threshold POKLT Percentage of Nominal Output Voltage for POK to be Low 90 % |
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Similar Description - LMK212BJ226MG-T |
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