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MC9S08PA32 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc |
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MC9S08PA32 Datasheet(HTML) 24 Page - Freescale Semiconductor, Inc |
24 / 35 page 6.3.2 Analog comparator (ACMP) electricals Table 13. Comparator electrical specifications C Characteristic Symbol Min Typical Max Unit D Supply voltage VDDA 2.7 — 5.5 V T Supply current (Operation mode) IDDA — 10 20 µA D Analog input voltage VAIN VSS - 0.3 — VDDA V P Analog input offset voltage VAIO — — 40 mV C Analog comparator hysteresis (HYST=0) VH — 15 20 mV C Analog comparator hysteresis (HYST=1) VH — 20 30 mV T Supply current (Off mode) IDDAOFF — 60 — nA C Propagation Delay tD — 0.4 1 µs 6.4 Communication interfaces 6.4.1 SPI switching specifications The serial peripheral interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes slew rate control is disabled and high drive strength is enabled for SPI output pins. Table 14. SPI master mode timing Nu m. Symbol Description Min. Max. Unit Comment 1 fop Frequency of operation fBus/2048 fBus/2 Hz fBus is the bus clock 2 tSPSCK SPSCK period 2 x tBus 2048 x tBus ns tBus = 1/fBus 3 tLead Enable lead time 1/2 — tSPSCK — 4 tLag Enable lag time 1/2 — tSPSCK — 5 tWSPSCK Clock (SPSCK) high or low time tBus - 30 1024 x tBus ns — 6 tSU Data setup time (inputs) 15 — ns — 7 tHI Data hold time (inputs) 0 — ns — 8 tv Data valid (after SPSCK edge) — 25 ns — 9 tHO Data hold time (outputs) 0 — ns — Table continues on the next page... Peripheral operating requirements and behaviors MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012. 24 Freescale Semiconductor, Inc. |
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