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CXD1265R Datasheet(PDF) 1 Page - Sony Corporation |
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CXD1265R Datasheet(HTML) 1 Page - Sony Corporation |
1 / 24 page Description The CXD1265R generates the timing pulses required by the CCD image sensors as well as signal processing circuits. Features • NTSC and PAL compatible • Compatible with digital and analog camera systems • Black-and-white mode compatible (EIA/CCIR compatible) • Electronic shutter function • H-driver • Standby function • Compatible with field/frame accumulation modes∗1, ∗2 ∗1 Characteristics of CCD image sensor are guaranteed by field accumulation. ∗2 Low speed shutter can not be used during frame accumulation mode. Applications CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX038BNA, ICX038BNB, ICX038BLA ICX039BNA, ICX039BNB, ICX039BLA ICX058AK, ICX058AKB, ICX058AL ICX059AK, ICX059AKB, ICX059AL Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD Vss – 0.5 to +7.0 V • Input voltage VI Vss – 0.5 to VDD + 0.5 V • Output voltage VO Vss – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C • Supply voltage VEE –5 to Vss V • Allowable power dissipation PD 500 mW Recommended Operating Conditions • Supply voltage VDD 5.0 ± 0.25 V • Operating temperature Topr –20 to +75 °C – 1 – CXD1265R E92611C52-ST CCD Camera Timing Generator Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin LQFP (Plastic) 8 15 16 17 18 19 20 21 24 25 28 40 56 4 5 6 7 9 11 12 13 14 23 36 61 22 37 41 42 43 44 45 46 57 59 60 62 GATE 1/2 VD INITIALIZE SYNC GEN 3 10 26 27 29 30 39 38 35 34 31 32 33 47 48 49 50 51 52 53 54 55 58 23 HD INITIALIZE 2 64 1 ADR . COUNT H – ROM LATCH ADR . COUNT V – ROM LATCH ADR . COUNT ROG – ROM LATCH MODE SET GATE GATE DRIVER HIGH-SPEED PULSE GENERATION CIRCUIT DECODER GATE COUNTER SHUT ROM MICROCOMPUTER CONTROLLER 63 VSS VDD HTSG VEE DECODER Block Diagram |
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