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CXB1581Q Datasheet(PDF) 10 Page - Sony Corporation |
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CXB1581Q Datasheet(HTML) 10 Page - Sony Corporation |
10 / 22 page – 10 – CXB1581Q 59 LPF_A External part connection pin — External loop filter connection. (See Notes on Operation and Fig. 1.) VEEP1 VCCP LPF_A LPF_B VEEP2 60 LPF_B External part connection pin — External loop filter connection. (See Notes on Operation and Fig. 1.) 61, 62, 78 VEEE Power supply 0V Negative power supplies for ECL I/O. VEEP1 VCCP LPF_A LPF_B VEEP2 64 63 EXCLK EXCLK∗ ECL input (differen -tial) Open External clock inputs. When ECLKSEL∗ is set to low level, the clock input to these pins is used as the transmission bit clock. EXCLK is biased to become low level when left open. VEEG VEEE EXCLK∗ EXCLK VCCE VCCG VCCE – 1.3V 66 65 SDIN SDIN∗ ECL input (differen -tial) ECL level Serial data inputs. When SDSEL is set to high level, the data input to these pins is output unmodified from SDOUT. VEEE SDIN∗ SDIN VCCE VEEG VCCG VCCE – 1.3V — Symbol Type Equivalent circuit Description Pin No. Typical pin I/O voltage |
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