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BF904AR Datasheet(PDF) 73 Page - NXP Semiconductors |
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BF904AR Datasheet(HTML) 73 Page - NXP Semiconductors |
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73 / 130 page  74 NXP Semiconductors RF Manual 16th edition 2.6.4 High-performance,small-sizepackagingenabledbyNXP'sleadlesspackageplatform andWL-CSPtechnology RF small-signal packaging is driven by two major trends which partly overlap ` Lower parasitics for better RF performance ` Smaller form factors for portable applications To cope with these trends, NXP uses several approaches ` For non-space-restricted applications the use of flat-pack packages instead of gull-wing versions reduces the parasitic impedance because of shorter lead length (e.g. SOT343F instead of SOT343). This results in better RF performance in the Ku and Ka bands (13-20GHz). To reduce PCB board space, a smaller version (SOT1206) is also available. SOT343 SOT343F SOT1206 ` For space-restricted applications there are two routes to reduce the form factor and parasitics: - Leadless package platform - Wafer Level Chip Scale Package (WL-CSP) technology The leadless package (UTLP) platform (>25 variants already released) is highly flexible with respect to package size, package height, and I/O pitch. For example, the 6-pin packages range in size from 1.45 x 1 x 0.5 mm with 0.5 mm pitch to 0.8 x 0.8 x 0.35 mm with 0.3 mm pitch. Package height of 0.25 mm is planned. Because of the compact size of the design, wire lengths and parasitic impedance are also restricted. The absence of leads further reduces the inductance. Wafer Level Chip Scale Package technology is ideally for RF functions where the I/O pitch has to fit within the chip area. With larger pitches and smaller designs (and thus little effective chip area), it is more cost-effective to do the fan-out using a leadless package instead of increasing the chip size. The absence of wires gives the lowest parasitic inductance available. SOT886 SOT891 SOT1208 0.65 x 0.44 x 0.29 mm (incl. 0.09 mm balls) 5 I/Os @ 0.22 mm pitch |
Similar Part No. - BF904AR |
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Similar Description - BF904AR |
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