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CXA3017R Datasheet(PDF) 35 Page - Sony Corporation |
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CXA3017R Datasheet(HTML) 35 Page - Sony Corporation |
35 / 83 page – 35 – CXA3017R • RGB output RGB outputs (Pins 40, 43 and 45) are inverted each horizontal line by the FRP pulse (internal pulse) supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center) of the output signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG CENTER (Pin 48)). In addition, the white level output is clipped at the limiter operation point that is set by the serial bus register WHITE LIM, and the black level output is clipped at the limiter operation point that is set by the serial bus register BLKLIM. Video IN FRP RGB OUT Black level limiter White level limiter White level limiter Black level limiter Vsig center 3) TG block • PLL and AFC circuits The TG block contains a PLL circuit phase comparator and frequency division counter and a VCO circuit, and comprises a PLL circuit. The PLL error detection signal is generated by the HSYNC block, and the integral value of the phase comparison output of the entire bottom of HSYNC and the internal frequency division counter becomes RPD (Pin 9). The CXA3017R controls the internal VCO with the RPD output to stabilize the oscillation frequency at 690fH (NTSC) or 716fH (PAL) for the LCX005BK/BKB and LCX024AK/AKB, and 1034fH (NTSC) or 1072fH (PAL) for the LCX009AK/AKB, LCX027AK/AKB and DCX501BK. The PLL of this system is adjusted by adjusting the serial bus register VCO so that the RPD output waveform is constant near VSYNC as shown in the figure Adjust to a horizontal waveform. Video signal RPD (Pin 9) Horizontal AFC adjustment • H position The horizontal display position can be set at 2fH intervals in 32 different ways by the serial bus settings. Note that the delay difference between the RGB signal and the drive pulse differs according to the board, so adjust the serial bus register H position so that the picture center matches the center of the LCD panel. |
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