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CY14MB064J1A Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY14MB064J1A Datasheet(HTML) 4 Page - Cypress Semiconductor |
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4 / 28 page  PRELIMINARY CY14MB064J1A/CY14MB064J2A CY14ME064J1A/CY14ME064J2A Document Number: 001-70393 Rev. *E Page 4 of 28 I2C Interface I2C bus consists of two lines – serial clock line (SCL) and serial data line (SDA) that carry information between multiple devices on the bus. I2C supports multi-master and multi-slave configurations. The data is transmitted from the transmitter to the receiver on the SDA line and is synchronized with the clock SCL generated by the master. The SCL and SDA lines are open-drain lines and are pulled up to VCC using resistors. The choice of pull-up resistor on the system depends on the bus capacitance and the intended speed of operation. The master generates the clock and all the data I/Os are transmitted in synchronization with this clock. The CY14MX064J supports up to 3.4 MHz clock speed on SCL line. Protocol Overview This device supports only a 7-bit addressable scheme. The master generates a START condition to initiate the communication followed by broadcasting a slave select byte. The slave select byte consists of a seven bit address of the slave that the master intends to communicate with and R/W bit indicating a read or a write operation. The selected slave responds to this with an acknowledgement (ACK). After a slave is selected, the remaining part of the communication takes place between the master and the selected slave device. The other devices on the bus ignore the signals on the SDA line till a STOP or Repeated START condition is detected. The data transfer is done between the master and the selected slave device through the SDA pin synchronized with the SCL clock generated by the master. I2C Protocol – Data Transfer Each transaction in I2C protocol starts with the master generating a START condition on the bus, followed by a seven bit slave address and eighth bit (R/W) indicating a read (1) or a write (0) operation. All signals are transmitted on the open-drain SDA line and are synchronized with the clock on SCL line. Each byte of data transmitted on the I2C bus is acknowledged by the receiver by holding the SDA line LOW on the ninth clock pulse. The request for write by the master is followed by the memory address and data bytes on the SDA line. The writes can be performed in burst-mode by sending multiple bytes of data. The memory address increments automatically after receiving /transmitting of each byte on the falling edge of 9th clock cycle. The new address is latched just prior to sending/receiving the acknowledgment bit. This allows the next sequential byte to be accessed with no additional addressing. On reaching the last memory location, the address rolls back to 0x0000 and writes continue. The slave responds to each byte sent by the master during a write operation with an ACK. A write sequence can be terminated by the master generating a STOP or Repeated START condition. A read request is performed at the current address location (address next to the last location accessed for read or write). The memory slave device responds to a read request by transmitting the data on the current address location to the master. A random address read may also be performed by first sending a write request with the intended address of read. The master must abort the write immediately after the last address byte and issue a Repeated START or STOP signal to prevent any write operation. The following read operation starts from this address. The master acknowledges the receipt of one byte of data by holding the SDA pin LOW for the ninth clock pulse. The reads can be terminated by the master sending a no-acknowledge (NACK) signal on the SDA line after the last data byte. The no-acknowledge signal causes the CY14MX064J to release the SDA line and the master can then generate a STOP or a Repeated START condition to initiate a new operation. Figure 2. System Configuration using Serial (I2C) nvSRAM Vcc SDA SCL Vcc Vcc 0 A 0 A 0 A A1 A1 A1 L C S L C S L C S SDA A D S A D S P W P W P W CY14MX064J #0 #1 #7 A2 A2 A2 Microcontroller CY14MX064J CY14MX064J RPmin = (VCC - VOLmax) / IOL RPmax = tr / (0.8473) * Cb |
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