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CY14B101P-SFXIT Datasheet(PDF) 26 Page - Cypress Semiconductor

Part # CY14B101P-SFXIT
Description  1-Mbit (128 K 횞 8) Serial SPI nvSRAM with Real Time Clock
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14B101P-SFXIT Datasheet(HTML) 26 Page - Cypress Semiconductor

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CY14B101P
Document Number: 001-44109 Rev. *M
Page 26 of 36
RTC Characteristics
Over the Operating Range
Parameter
Description
Min
Typ[13]
Max
Units
VRTCbat
RTC battery pin voltage
1.8
3.0
3.6
V
IBAK
[14]
RTC backup current
TA (min)
0.35
µA
25 °C
–0.35–
µA
TA (max)
0.5
µA
VRTCcap
[15]
RTC capacitor pin voltage
TA (min)
1.6
3.6
V
25 °C
1.5
3.0
3.6
V
TA (max)
1.4
3.6
V
tRTCp
RTC processing time from end of ‘W’ bit set to ‘0’
350
µs
tOCS
RTC oscillator time to start
1
2
sec
RBKCHG
RTC backup capacitor charge current-limiting resistor
350
850
AC Switching Characteristics
Over the Operating Range
Parameters [16]
Description
40 MHz
25 MHz
(RDRTC Instruction)[17]
Unit
Cypress
Parameter
Alt. Parameter
Min
Max
Min
Max
fSCK
fSCK
Clock frequency, SCK
40
25
MHz
tCL
tWL
Clock pulse width LOW
11
18
ns
tCH
tWH
Clock pulse width HIGH
11
18
ns
tCS
tCE
CS HIGH time
20
20
ns
tCSS
tCES
CS setup time
10
10
ns
tCSH
tCEH
CS hold time
10
10
ns
tSD
tSU
Data in setup time
5
5
ns
tHD
tH
Data in hold time
5
5
ns
tHH
tHD
HOLD hold time
5
5
ns
tSH
tCD
HOLD setup time
5
5
ns
tCO
tV
Output valid
9
15
ns
tHHZ
[18]
tHZ
HOLD to output HIGH-Z
15
15
ns
tHLZ
[18]
tLZ
HOLD to output LOW-Z
15
15
ns
tOH
tHO
Output hold time
0
0
ns
tHZCS
tDIS
Output disable time
25
25
ns
Notes
13. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
14. Current drawn from either VRTCcap or VRTCbat when VCC < VSWITCH.
15. If VRTCcap > 0.5 V or if no capacitor is connected to VRTCcap pin, the oscillator will start in tOCS time. If a backup capacitor is connected and VRTCcap < 0.5 V, the
capacitor must be allowed to charge to 0.5 V for oscillator to start.
16. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 24.
17. Applicable for RTC opcode cycles, address cycles and dataout cycles.
18. These parameters are guaranteed by design and are not tested.


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