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CY7C680363-56LTXC Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY7C680363-56LTXC Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 40 page  CY7C68033/CY7C68034 Document Number: 001-04247 Rev. *J Page 5 of 40 8051 Clock Frequency NX2LP-Flex has an on-chip oscillator circuit that uses an external 24 MHz (±100 ppm) crystal with the following characteristics: ■ Parallel resonant ■ Fundamental mode ■ 500 W drive level ■ 12 pF (5% tolerance) load capacitors. An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY, and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically Figure 3. Crystal Configuration Special Function Registers Certain 8051 SFR addresses are populated to provide fast access to critical NX2LP-Flex functions. These SFR additions are shown in Table 1 on page 6. Bold type indicates non-standard, enhanced 8051 registers. The two SFR rows that end with ‘0’ and ‘8’ contain bit-addressable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not implemented in NX2LP-Flex. Because of the faster and more efficient SFR addressing, the NX2LP-Flex I/O ports are not addressable in external RAM space (using the MOVX instruction). I2C Bus NX2LP supports the I2C bus as a master only at 100/400 kHz. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3 V, even if no I2C device is connected. The I2C bus is disabled at startup and only available for use after the initial NAND access. 12 pF 12 pF 24 MHz 20 × PLL C1 C2 12-pF capacitor values assumes a trace capacitance of 3 pF per side on a four-layer FR4 PCA |
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