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CY8C29466 Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C29466 Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 35 page CY8C29466, CY8C29666 Document Number: 38-12026 Rev. *M Page 3 of 35 PSoC Functional Overview The PSoC programmable system-on-chip family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated in the Logic Block Diagram on page 1, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global buses allow all the device resources to be combined into a complete custom system. The PSoC CY8C29x66 family can have up to six I/O ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks. The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO. The M8C CPU core is a powerful processor with speeds up to 12 MHz, providing a two MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep Timer and Watch Dog Timer (WDT). Memory includes 32K of Flash for program storage and 2K of SRAM for data storage. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to ±4% over temperature and voltage. A low power 32 kHz internal low speed oscillator (ILO) is provided for the Sleep Timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital resources, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt. The Digital System The Digital System is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user modules. Digital peripheral configurations include those listed here. ■ PWMs (8- and 16-bit) ■ PWMs with Dead Band (8- and 16-bit) ■ Counters (8 to 32 bit) ■ Timers (8 to 32 bit) ■ Full or Half-Duplex 8-bit UART with selectable parity (up to 4 Full-Duplex or 8 Half-Duplex) ■ SPI master and slave (up to 8 total) ■ I 2C master, slave, or multi-master ■ Cyclical Redundancy Checker/Generator (16 bit) ■ IrDA (up to 4) ■ Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 5. Figure 1. Digital System Block Diagram DIGITAL SYSTEM To System Bus Digital Clocks From Core Digital PSoC Block Array To Analog System 8 8 8 8 Row 1 DBB10 DBB11 DCB12 DCB13 4 4 Row 2 DBB20 DBB21 DCB22 DCB23 4 4 Row 0 DBB00 DBB01 DCB02 DCB03 4 4 Row 3 DBB30 DBB31 DCB32 DCB33 4 4 GIE[7:0] GIO[7:0] GOE[7:0] GOO[7:0] Global Digital Interconnect Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 |
Similar Part No. - CY8C29466_12 |
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Similar Description - CY8C29466_12 |
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