CY7C25632KV18-550BZXI datasheet(7/31 Pages) CYPRESS

Part #	CY7C25632KV18-550BZXI

Description	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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CY7C25632KV18

CY7C25652KV18

Document Number: 001-66482 Rev. *C

Page 7 of 31

the lower 18-bit write data register, provided BWS[1:0] are both

asserted active. On the subsequent rising edge of the negative

input clock (K) the information presented to D[17:0] is also stored

into the write data register, provided BWS[1:0] are both asserted

active. This process continues for one more cycle until four 18-bit

words (a total of 72 bits) of data are stored in the SRAM. The

72 bits of data are then written into the memory array at the

specified location. Therefore, write accesses to the device can

not be initiated on two consecutive K clock rises. The internal

logic of the device ignores the second write request. Write

accesses can be initiated on every other rising edge of the

positive input clock (K). Doing so pipelines the data flow such

that 18 bits of data can be transferred into the device on every

rising edge of the input clocks (K and K).

When deselected, the write port ignores all inputs after the

pending write operations have been completed.

Byte Write Operations

Byte write operations are supported by the CY7C25632KV18. A

write operation is initiated as described in the section Write

Operations on page 6. The bytes that are written are determined

by BWS0 and BWS1, which are sampled with each set of 18-bit

data words. Asserting the appropriate Byte Write Select input

during the data portion of a write latches the data being

presented and writes it into the device. Deasserting the Byte

Write Select input during the data portion of a write enables the

data stored in the device for that byte to remain unaltered. This

feature can be used to simplify read, modify, or write operations

to a byte write operation.

Concurrent Transactions

The read and write ports on the CY7C25632KV18 operates

completely independently of one another. As each port latches

the address inputs on different clock edges, the user can read or

write to any location, regardless of the transaction on the other

port. If the ports access the same location when a read follows a

write in successive clock cycles, the SRAM delivers the most

recent information associated with the specified address

location. This includes forwarding data from a write cycle that

was initiated on the previous K clock rise.

Read access and write access must be scheduled such that one

transaction is initiated on any clock cycle. If both ports are

selected on the same K clock rise, the arbitration depends on the

previous state of the SRAM. If both ports are deselected, the

read port takes priority. If a read was initiated on the previous

cycle, the write port takes priority (as read operations can not be

initiated on consecutive cycles). If a write was initiated on the

previous cycle, the read port takes priority (as write operations

can not be initiated on consecutive cycles). Therefore, asserting

both port selects active from a deselected state results in

alternating read or write operations being initiated, with the first

access being a read.

Depth Expansion

The CY7C25632KV18 has a port select input for each port. This

enables for easy depth expansion. Both port selects are sampled

on the rising edge of the positive input clock only (K). Each port

select input can deselect the specified port. Deselecting a port

does not affect the other port. All pending transactions (read and

write) are completed before the device is deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin

on the SRAM and VSS to allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5 × the value of the

intended line impedance driven by the SRAM, the allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15% is between 175

 and 350 , with V

DDQ =1.5 V. The

output impedance is adjusted every 1024 cycles upon power up

to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR II+ to simplify data capture

on high-speed systems. Two echo clocks are generated by the

QDR II+. CQ is referenced with respect to K and CQ is

referenced with respect to K. These are free-running clocks and

are synchronized to the input clock of the QDR II+. The timing

for the echo clocks is shown in the Switching Characteristics on

page 24.

Valid Data Indicator (QVLD)

QVLD is provided on the QDR II+ to simplify data capture on high

speed systems. The QVLD is generated by the QDR II+ device

along with data output. This signal is also edge-aligned with the

echo clock and follows the timing of any data pin. This signal is

asserted half a cycle before valid data arrives.

On-Die Termination (ODT)

These devices have an On-Die Termination feature for Data

inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K

and K). The termination resistors are integrated within the chip.

The ODT range selection is enabled through ball R6 (ODT pin).

The ODT termination tracks value of RQ where RQ is the resistor

tied to the ZQ pin. ODT range selection is made during power up

initialization. A LOW on this pin selects a low range that follows

RQ/3.33 for 175

< RQ < 350 (where RQ is the resistor tied

to ZQ pin)

A HIGH on this pin selects a high range that follows

RQ/1.66 for 175

< RQ < 250 (where RQ is the resistor tied

to ZQ pin). When left floating, a high range termination value is

selected by default. For a detailed description on the ODT

implementation, refer to the application note, On-Die Termination

for QDRII+/DDRII+ SRAMs.

PLL

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power up, when the DOFF is tied HIGH, the PLL is locked after

20

s of stable clock. The PLL can also be reset by slowing or

stopping the input clocks K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 20

s after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in QDR I mode (with one cycle latency and a longer

access time). For information, refer to the application note, PLL

Considerations in QDRII/DDRII/QDRII+/DDRII+.

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