CY7C1354CV25

CY7C1356CV25

Document Number: 38-05537 Rev. *M

Page 11 of 33

Partial Truth Table for Read/Write

The partial truth table for Read/Write for CY7C1354CV25 follows. [9, 10, 11, 12]

Function (CY7C1354CV25)

WE

Read

H

X

X

X

X

Write

– no bytes written

L

H

H

H

H

Write byte a–

H

H

H

L

H

H

L

H

Write bytes b, a

L

H

H

L

L

Write byte c –

H

L

H

H

Write bytes c, a

L

H

L

H

L

Write bytes c, b

L

H

L

L

H

Write bytes c, b, a

L

H

L

L

L

Write byte d –

L

H

H

H

Write bytes d, a

L

L

H

H

L

Write bytes d, b

L

L

H

L

H

Write bytes d, b, a

L

L

H

L

L

Write bytes d, c

L

L

L

H

H

Write bytes d, c, a

L

L

L

H

L

Write bytes d, c, b

L

L

L

L

H

Write all bytes

LLL

LL

Partial Truth Table for Read/Write

The partial truth table for Read/Write for CY7C1356CV25 follows. [9, 10, 11, 12]

Function (CY7C1356CV25)

WE

Read

H

x

x

Write – no bytes written

L

H

H

Write byte a

H

L

L

H

Write both bytes

L

L

L

Notes

9. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies

that the desired byte write selects are asserted, see Write Cycle Description table for details.

11. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.