CY7C1350G

Document Number: 38-05524 Rev. *L

Page 11 of 21

Automatic CE power-down

current – CMOS inputs

5-ns cycle,

200 MHz

–95

mA

7.5-ns cycle,

133 MHz

–75

mA

Automatic CE power-down

current – TTL inputs

All speeds

–

45

mA

Over the Operating Range

Description

Test Conditions

Min

Max

Unit

Capacitance

Parameter [13]

Description

Test Conditions

100-pin TQFP

Max

119-ball BGA

Max

Unit

Input capacitance

55

pF

Clock input capacitance

5

5

pF

Input/Output capacitance

5

7

pF

Thermal Resistance

Parameter [13]

Description

Test Conditions

100-pin TQFP

Package

119-ball BGA

Package

Unit

Thermal resistance

(junction to ambient)

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51.

30.32

34.1

°C/W

Thermal resistance

(junction to case)

6.85

14.0

°C/W

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms

OUTPUT

R = 317



R = 351



5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

3.3 V

ALL INPUT PULSES

GND

90%

10%

90%

10%

 1 ns

 1 ns

(c)

OUTPUT

R = 1667



R =1538



5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

2.5 V

ALL INPUT PULSES

GND

90%

10%

90%

10%

 1 ns

 1 ns

(c)

3.3 V I/O Test Load

2.5 V I/O Test Load

Note

13. Tested initially and after any design or process changes that may affect these parameters.