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CY7C1350G-133AXC Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY7C1350G-133AXC Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 21 page CY7C1350G Document Number: 38-05524 Rev. *L Page 11 of 21 ISB3 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, VIN 0.3 V or VIN > VDDQ – 0.3 V, f = fMAX = 1/tCYC 5-ns cycle, 200 MHz –95 mA 7.5-ns cycle, 133 MHz –75 mA ISB4 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, VIN VIH or VIN VIL, f = 0 All speeds – 45 mA Electrical Characteristics (continued) Over the Operating Range Parameter [11, 12] Description Test Conditions Min Max Unit Capacitance Parameter [13] Description Test Conditions 100-pin TQFP Max 119-ball BGA Max Unit CIN Input capacitance TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 3.3 V 55 pF CCLK Clock input capacitance 5 5 pF CI/O Input/Output capacitance 5 7 pF Thermal Resistance Parameter [13] Description Test Conditions 100-pin TQFP Package 119-ball BGA Package Unit JA Thermal resistance (junction to ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 30.32 34.1 °C/W JC Thermal resistance (junction to case) 6.85 14.0 °C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms OUTPUT R = 317 R = 351 5pF INCLUDING JIG AND SCOPE (a) (b) OUTPUT RL = 50 Z0 = 50 VT = 1.5 V 3.3 V ALL INPUT PULSES VDDQ GND 90% 10% 90% 10% 1 ns 1 ns (c) OUTPUT R = 1667 R =1538 5pF INCLUDING JIG AND SCOPE (a) (b) OUTPUT RL = 50 Z0 = 50 VT = 1.25 V 2.5 V ALL INPUT PULSES VDDQ GND 90% 10% 90% 10% 1 ns 1 ns (c) 3.3 V I/O Test Load 2.5 V I/O Test Load Note 13. Tested initially and after any design or process changes that may affect these parameters. |
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