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CY7C1328G-133AXI Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C1328G-133AXI Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 22 page  CY7C1328G Document Number: 38-05523 Rev. *J Page 8 of 22 Truth Table The Truth Table for part CY7C1328G is as follows. [1, 2, 3, 4, 5] Operation Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected cycle, power-down None H X X L X L X X X L–H Tristate Deselected cycle, power-down None L L X L L X X X X L–H Tristate Deselected cycle, power-down None L X H L L X X X X L–H Tristate Deselected cycle, power-down None L L X L H L X X X L–H Tristate Deselected cycle, power-down None L X H L H L X X X L–H Tristate ZZ mode, power-down None X X X H X X X X X X Tristate Read cycle, begin burst External L H L L L X X X L L–H Q Read cycle, begin burst External L H L L L X X X H L–H Tristate Write cycle, begin burst External L H L L H L X L X L–H D Read cycle, begin burst External L H L L H L X H L L–H Q Read cycle, begin burst External L H L L H L X H H L–H Tristate Read cycle, continue burst Next X X X L H H L H L L–H Q Read cycle, continue burst Next X X X L H H L H H L–H Tristate Read cycle, continue burst Next H X X L X H L H L L–H Q Read cycle, continue burst Next H X X L X H L H H L–H Tristate Write cycle, continue burst Next X X X L H H L L X L–H D Write cycle, continue burst Next H X X L X H L L X L–H D Read cycle, suspend burst Current X X X L H H H H L L–H Q Read cycle, suspend burst Current X X X L H H H H H L–H Tristate Read cycle, suspend burst Current H X X L X H H H L L–H Q Read cycle, suspend burst Current H X X L X H H H H L–H Tristate Write cycle, suspend burst Current X X X L H H H L X L–H D Write cycle, suspend burst Current H X X L X H H L X L–H D Notes 1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more byte write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all byte write enable signals (BWA, BWB), BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). |
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Similar Description - CY7C1328G-133AXI |
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