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CY7C1328G-133AXI Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C1328G-133AXI
Description  4-Mbit (256 K 횞 18) Pipelined DCD Sync SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1328G-133AXI Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY7C1328G
Document Number: 38-05523 Rev. *J
Page 6 of 22
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1328G supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486
 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW[A:B]) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Synchronous chip selects CE1, CE2, CE3 and an asynchronous
output enable (OE) provide for easy bank selection and output
tristate control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs is stored into
the address advancement logic and the address register while
being presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and onto the data bus within tCO if OE
is active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its outputs
are always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
The CY7C1328G is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tristate immediately after
the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
BWE, and BW[A:B]) and ADV inputs are ignored during this first
cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, then the write operation is controlled by BWE and BW[A:B]
signals. The CY7C1328G provides byte write capability that is
described in the Write Cycle Description table. Asserting the byte
write enable input (BWE) with the selected byte write input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations.
Because the CY7C1328G is a common I/O device, the output
enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tristate the output drivers. As a
safety precaution, DQ are automatically tri-stated whenever a
write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) chip select is asserted active, and (4) the appropriate
combination of the write inputs (GW, BWE, and BW[A:B]) are
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
written into the corresponding address location in the memory
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1328G is a common I/O device, the output
enable (OE) must be deasserted HIGH before presenting data
to the DQX inputs. Doing so will tristate the output drivers. As a
MODE
31
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode pin has an internal pull-up.
NC
1, 2, 3, 6, 7,
14, 16, 25, 28,
29, 30, 38, 39,
42, 43, 51, 52,
53, 56, 57, 66,
75, 78, 79, 95,
96
No connects. Not internally connected to the die.
Pin Definitions (continued)
Pin
TQFP
Type
Description


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