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R262 Datasheet(PDF) 4 Page - ON Semiconductor |
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R262 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 28 page BelaSigna R262 http://onsemi.com 4 Table 2. ELECTRICAL CHARACTERISTICS (The typical parameters in Table 2 were measured at 20°C with a clean 3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified for all process corners but not tested on every part.) Parameter Symbol Test Conditions / Notes Min Typ Max Unit Screened DIGITAL MICROPHONE OUTPUT DMIC input clock frequency With preset 0 selected on CLOCK_SEL (Note 3) 2.048 MHz With preset 3 selected on CLOCK_SEL (Note 3) 2.4 MHz With preset 4 selected on CLOCK_SEL (Note 3) 2.8 MHz With preset 5 selected on CLOCK_SEL (Note 3) 3.072 MHz Clock duty cycle Any clock configuration 40 50 60 % Input clock jitter Maximum allowed jitter on the DMIC_CLK 10 ns Clock to output transition time DMIC_OUT 10 20 50 ns ANALOG OUTPUT STAGE Signal Range Vout One single ended DAC used 0 2 Vpp Two DACs used as one differential output 0 4 Vpp Attenuator gain tolerance −2 2 dB Output impedance Rout @ 12 dB output attenuation 19 kW l @ 0 dB output attenuation 3 kW Channel cross coupling @ 1 kHz −50 dB Analog Filter cut−off frequency LPF Enabled (default) 13.0 13.5 kHz LPF Disabled 25 26 kHz Analog Filter passband flatness −1 1 dB Analog filter stopband attenuation > 60 kHz 90 dB Digital Filter cut−off frequency Fs/2 kHz Digital Filter cut−off stopband attenuation 80 dB Total Harmonic Distortion + Noise (Peak value) THDN 63 65 dB l Dynamic Range DR 78 80 dB l Noise Floor 70 100 mV l DIRECT DIGITAL OUTPUT (available only through custom configuration) Supply voltage VBATRCVR 1.8 3.3 3.63 V Signal Range Vout Differential Output @ 1 kHz 0 2*VBAT RCVR Vpp Single ended Output @ 1 kHz 0 VBAT RCVR Vpp Output Impedance Rout Load between 1 mA and 30 mA @ 0°C 2.5 10 W Maximum Current 25 mA Total Harmonic Distortion + Noise (Peak value) THDN 64 70 dB l 3. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this document and in the BelaSigna R262 Communications and Configuration Guide for more information on custom mode usage. |
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