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SIC778ACD-T1-GE3 Datasheet(PDF) 6 Page - Vishay Siliconix |
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SIC778ACD-T1-GE3 Datasheet(HTML) 6 Page - Vishay Siliconix |
6 / 13 page www.vishay.com 6 Document Number: 63808 S12-1132-Rev. B, 21-May-12 Vishay Siliconix SiC778A This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: powerictechsupport@vishay.com Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC778A also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20.2 k resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET. FUNCTIONAL BLOCK DIAGRAM Figure 3: SiC778 Functional Block Diagram DEVICE TRUTH TABLE DSBL# SMOD PWM GH GL Open XX L L L XX L L H LLLL H LH HL H HHH L H HL L H H LTri-state L L H HTri-state L L |
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