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SN65LVDS86ADGGRQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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SN65LVDS86ADGGRQ1 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 17 page  SN65LVDS86A-Q1 www.ti.com SLLS768A – AUGUST 2006 – REVISED JANUARY 2012 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Positive-going differential input VIT+ 100 mV threshold voltage Negative-going differential input VIT– –100 mV threshold voltage(2) VOH High-level output voltage IOH = –4 mA 2.4 V VOL Low-level output voltage IOL = 4 mA 0.4 V All inputs to Disabled, 280 μA GND Enabled, AnP = 1 V, 33 40 AnM = 1.4 V, tc = 15.38 ns ICC Quiescent current (average) Enabled, CL = 8 pF, 43 mA Grayscale pattern (see Figure 3), tc = 15.38 ns Enabled, CL = 8 pF, 68 Worst-case pattern (see Figure 4), tc = 15.38 ns IIH High-level input current (SHTDN) VIH = VCC ±20 μA IIL Low-level input current (SHTDN) VIL = 0 ±25 μA II Input current A inputs 0 ≤ VI ≤ 2.4 V ±20 μA IOZ High-impedance output current VO = 0 or VCC ±10 μA (1) All typical values are at VCC = 3.3 V, TA = 25°C. (2) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going input voltage threshold only. Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tsu Setup time, D0 –D20 to CLKOUT↓ 5 ns CL = 8 pF, See Figure 5 th Data hold time, CLKOUT ↓ to D0–D20 5 ns tc = 15.38 ns (±0.2%), t(RSKM) Receiver input skew margin(2) (see Figure 7) 550 700 ps |Input clock jitter| < 50 ps,(3) VCC = 3.3 V, td Delay time, CLKIN ↑ to CLKOUT↓ (see Figure 7) 3 5 7 ns tc = 15.38 ns (±0.2%), TA = 25°C ten Enable time, SHTDN to phase lock See Figure 7 1 ms tdis Disable time, SHTDN to off state See Figure 8 400 ns tt Transition time, output (10% to 90% tr or tf) (data only) CL = 8 pF 3 ns tt Transition time, output (10% to 90% tr or tf) (clock only) CL = 8 pF 1.5 ns tw Pulse duration, output clock 0.50 tc ns (1) All typical values are at VCC = 3.3 V, TA = 25°C. (2) The parameter t(RSKM) is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this parameter at clock periods other than 15.38 ns can be calculated from tRSKM = tc/14 – 550 ps. (3) |Input clock jitter| is the magnitude of the change in input clock period. Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN65LVDS86A-Q1 |
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