SN54LS224A, SN74LS224A

16

× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

WITH 3-STATE OUTPUTS

SDLS023E – JANUARY 1991 – REVISED APRIL 2003

1

POST OFFICE BOX 655303

Outputs

Board Layout

Ceramic (J) 300-mil DIPs, and Ceramic Chip

Carriers (FK)

description

The SN54LS224A and SN74LS224A 64-bit,

low-power Schottky memories are organized as

16 words by 4 bits each. They can be expanded

in multiples of 15m + 1 words or 4n bits, or both

(where n is the number of packages in the vertical

array and m is the number of packages in the

horizontal array); however, some external gating

is required. For longer words, the input-ready (IR)

signals

of

the

first-rank

packages

and

output-ready (OR) signals of the last-rank

packages

must

be

ANDed

for

proper

synchronization.

A first-in, first-out (FIFO) memory is a storage

device that allows data to be written to and read

from its array at independent data rates. These

FIFOs are designed to process data at rates up to

10 MHz in a bit-parallel format, word by word.

The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of

LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of

UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked

out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory

is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.

IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty

and UNCK is high.

A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low

to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting, with respect to

the data inputs, and are at high impedance when the output-enable (OE) input is low. OE does not affect the

IR and OR outputs.

The SN74LS224A is characterized for operation from 0

°C to 70°C. The SN54LS224A is characterized over the

full military temperature range of –55

°C to 125°C.

18

17

14

OR

Q0

NC

Q1

Q2

LDCK

D0

NC

D1

D2

OE

IR

LDCK

D0

D1

D2

D3

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

UNCK

OR

Q0

Q1

Q2

Q3

CLR

SN54LS224A ...J PACKAGE

SN74LS224A ...N PACKAGE

(TOP VIEW)

19

20

1

32

16

15

13

12

11

910

5

4

6

7

8

SN54LS224A . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.