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TM8SK64JPU Datasheet(PDF) 7 Page - Texas Instruments |
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TM8SK64JPU Datasheet(HTML) 7 Page - Texas Instruments |
7 / 13 page TM8SK64JPU 8388608 BY 64BIT SYNCHRONOUS DYNAMIC RAM MODULE SODIMM SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements†‡ ’8SK64JPU-10 UNIT MIN MAX UNIT tCK2 Cycle time, CK CAS latency = 2 15 ns tCK3 Cycle time, CK CAS latency = 3 10 ns tCH Pulse duration, CK high 3 ns tCL Pulse duraction, CK low 3 ns tAC2 Access time, CK high to data out (see Note 11) CAS latency = 2 9 ns tAC3 Access time, CK high to data out (see Note 11) CAS latency = 3 8 ns tOH Hold time, CK high to data out 3 ns tLZ Delay time, CK high to DQ in low−impedance state (see Note 12) 1 ns tHZ Delay time, CK high to DQ in high−impedance state (see Note 13) 8 ns tIS Setup time, address, control, and data input 3 ns tIH Hold time, address, control, and data input 1 ns tIH Hold time, address, control, and data input 1 ns tCESP Power down/self−refresh exit time 10 ns tRAS Delay time, ACTV command to DEAC or DCAB command 50 100000 ns tRC Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command 80 ns tRCD Delay time ACTV command to READ, READ−P, WRT, or WRT−P command (see Note 14) 30 ns tRP Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 30 ns tRRD Delay time, ACTV command in one bank to ACTV command in the other bank 20 ns tRSA Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 20 ns tAPR Final data out of READ−P operation to ACTV, MRS, SLFR, or REFR command tRP − (CL−1)* tCK ns tAPW Final data in of WRT−P operation to ACTV, MRS, SLFR, or REFR command tRP + 1 tCK ns tWR Delay time, final data in of WRT operation to DEAC or DCAB command 10 ns tT Transition time 1 5 ms † All references are made to the rising transition of CK unless otherwise noted. ‡ Specifications in this table represent a single SDRAM device. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. |
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