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SN74LV221AQPWRQ1 Datasheet(PDF) 3 Page - Texas Instruments |
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SN74LV221AQPWRQ1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 14 page A B CLR Q Q tw tw Rext/Cext tw SN74LV221A-Q1 www.ti.com SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 INPUT/OUTPUT TIMING DIAGRAM Absolute Maximum Ratings (1) over operating free-air temperature (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range(2) –0.5 7 V VO Output voltage range in high or low state(2) (3) –0.5 VCC + 0.5 V VO Output voltage range in power-off state(2) –0.5 7 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND ±50 mA θJA Package thermal impedance(4) 108 °C/W Human-Body Model 2 (H2) kV ESD rating(5) Charged-Device Model 1 (C5) Machine Model 200 (M3) V Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) This value is limited to 5.5 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) ESD protection level per AEC Q100 classification Copyright © 2005–2008, Texas Instruments Incorporated 3 |
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