TX517

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SLOS725A

– SEPTEMBER 2011 – REVISED JANUARY 2012

PIN FUNCTIONS

PIN NAME

DESCRIPTION

SUPPLIES

VAAx

Input Logic Supply (+2.5V)

VDD

+5V Driver Supply

VEE

–5V Driver Supply

HV0A, HV0B

Positive Supply of Low-voltage FET Output stage; Channel A and B

LV0A, LV0B

Negative Supply of Low-voltage FET Output stage; Channel A and B

HV2A, HV2B

Positive Supply of Intermediate voltage FET Output stage; this stage includes an internal de-glitcher

circuit.Channel A and B

LV2A, LV2B

Negative Supply of Intermediate voltage FET Output stage; this stage includes an internal de-glitcher

circuit.Channel A and B

HV1A, HV1B

Positive Supply of High-voltage FET Output stage; Channel A and B

LV1A, LV1B

Negative Supply of High-voltage FET Output stage; Channel A and B

VCWA, VCWB

Supply connections for CW FET output stage; Channel A and B

GND

Ground connection; Driver

GNDCWA, GNDCWB

Ground connection for CW FET output stage of Channel A and B

BIAS

Connect to VAA (+2.5V); used for internal biasing; high-impedance input

INPUTS

INP0A, INP0B

Logic input signal for the Low-voltage P-FET stage of channel A and B; Low = ON, High = OFF. Controls

HV0A, HV0B. High impedance input.

INN0A, INN0B

Logic input signal for the Low-voltage N-FET stage of channel A and B; Low = OFF, High = ON. Controls

LV0A, LV0B. High impedance input.

INP2A, INP2B

Logic input signal for the Intermediate voltage P-FET stage of channel A and B; Low = ON, High = OFF.

Controls HV2A, HV2B. High impedance input.

INN2A, INN2B

Logic input signal for the Intermediate Voltage N-FET stage of channel A and B; Low = OFF, High = ON.

Controls LV2A, LV2B. High impedance input.

INP1A, INP1B

Logic input signal for the High-voltage P-FET stage of channel A and B; Low = ON, High = OFF. Controls

HV1A, HV1B. High impedance input.

INN1A, INN1B

Logic input signal for the High-voltage N-FET stage of channel A and B; Low = OFF, High = ON. Controls

LV1A, LV1B. High impedance input.

CWINA

CW gate input signal for A output. An input

‘1’ means that current sinks from OUTA. An input ‘0’ means that

current sources from OUTA. This pin directly accesses the output A CW FET gates.

CWINB

CW gate input signal for B output. An input

‘1’ means that current sinks from OUTB. An input ‘0’ means that

current sources from OUTB. This pin directly accesses the output B CW FET gates.

EN

Logic Input for non-CW path; use the Enable-pin to select between input data being latched or transparent

operation. Low = input data will be retimed by the internal (T

&H) at the rate of the applied clock at PCLKIN.

High = use this mode when operating the TX517 without a clock. When High (1) the input data will bypass the

(T

&H). This pin is a common control for Channel A and B. High impedance input.

PDM

Power-down control input non-CW path; Low = power-down, High = normal operation. The PDM-pin controls

the voltage translation circuits which draw some quiescent power. This pin is a common control for Channel A

and B. High impedance input.

PCLKIN

Clock input for usage in latch (T

&H) mode. When clock signal is high, the (T&H) circuit is in track mode. When

clock signal is low, the (T

&H) is in hold mode. This pin is a common clock input for both Channel A and B. High

impedance input.

OUTPUTS

OUTA

Output Channel A

OUTB

Output Channel B

Copyright

© 2011–2012, Texas Instruments Incorporated

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Product Folder Link(s): TX517