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TNETA1585PCM Datasheet(PDF) 5 Page - Texas Instruments

Part No. TNETA1585PCM
Description  ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TNETA1585PCM Datasheet(HTML) 5 Page - Texas Instruments

 
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TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
receive-UTOPIA interface
TERMINAL
RESET
NAME
NO.
PGF
NO.
PCM
I/O
RESET
STATE
DESCRIPTION
RXCLK
26
24
I (TTL)
I
Receive clock. RXCLK is the data transfer/synchronization clock for
synchronizing transfers on RXDATA.
22
20 18
20
RXDATA7–
20–18
16
20
18–15
I (TTL)
I
Receive data Eight bit data lines RXDATA7 is the most significant bit
RXDATA7
RXDATA0
14
12
13–12
10
I (TTL)
I
Receive data. Eight-bit data lines. RXDATA7 is the most significant bit.
12
10
10
RXCLAV
24
22
I (TTL)
I
Receive-cell available. RXCLAV is an indication that a transfer of a complete
cell can be accepted.
RXEN
25
23
I (TTL)
I
Receive enable. RXEN indicates to the TNETA1585 when RXDATA contains
a valid byte.
RXSOC
23
21
I (TTL)
I
Receive start of cell. RXSOC is received by the device when RXDATA contains
the first valid byte of the cell.
parameter-memory interface
TERMINAL
RESET
NAME
NO.
PGF
NO.
PCM
I/O
RESET
STATE
DESCRIPTION
171
169–167
165
155
153–151
PMAD15–
165
163–162
153–151
149–147
O (CMOS)
Low
Parameter-memory address. PMAD15–PMAD0 provides a 16-bit
PMAD15
PMAD0
159–157
155 153
145–143
141 139
O (CMOS)
Low
y
physical address to the parameter memory.
155–153
151–150
141–139
137–135
151 150
148
137 135
143
141 139
141–139
137 135
131
137–135
133–131
129–127
133 131
129–127
125–123
121 119
125–123
121
121–119
117–115
PMDATA31–
121
119 118
117 115
113–111
I/O
Low
Parameter-memory data. PMDATA31–PMDATA0 provides 32-bit data
PMDATA31
PMDATA0
119–118
115–113
109–107
10
103
(TTL/CMOS)
Low
y
to/from the parameter memory.
115 113
111–109
105–103
101 99
107–106
104
101–99
97–95
104
102
97 95
93–91
102
100–99
89
100 99
97
PMWE
146
133
O (CMOS)
High
Parameter-memory write enable. The address and data are valid when
PMWE is low.
PMAD15
172
156
O (CMOS)
High
Inverse of PMAD15. PMAD15 can be used with PMAD15 to provide
SRAM bank switching.
PMOE
144
132
O (CMOS)
High
Parameter-memory output enable. The PMAD15–PMAD0 address is
valid when PMOE is low. Data is read into the TNETA1585 on the rising
edge of PMOE.


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