TMS29F002T, TMS29F002B

262144 BY 8-BIT

FLASH MEMORIES

SMJS848 – AUGUST 1997

9

POST OFFICE BOX 1443

program command (continued)

Programming can be performed at any address location in any sequence. When erased, all bits are in a

logic-high state. Logic lows are programmed into the device. Only an erase operation can change bits from logic

lows to logic highs. Attempting to program a 1 into a bit that has been programmed previously to a 0 causes

the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (DQ5) to

a logic-high state. The automatic-programming operation is complete when the data on (DQ7) is equivalent to

the data written to this bit, at which time the device returns to the read mode and addresses are no longer

latched. Figure 5 shows a flowchart of the typical device-programming operation.

chip-erase command

Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup

state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command. This

command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge

of WE starts the chip-erase operation. Any further commands written to the device during the chip-erase

operation are ignored.

The embedded chip-erase function automatically provides voltage and timing needed to program and to verify

all the memory cells prior to electrical erase and then erases and verifies the cell margin automatically without

programming the memory cells prior to erase.

Figure 8 shows a flow chart for the typical chip-erase device operation.

sector-erase command

Sector erase is a six-bus-cycle command sequence. The first three bus cycles cause the device to go into the

erase-setup state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the sector-erase

command and the sector-address location to be erased. Any address location within the desired sector can be

used. The addresses are latched on the falling edge of WE and the sector-erase command (30h) is latched on

the rising edge of WE in the sixth bus cycle. After a delay of 80

µs from the rising edge of WE, the sector-erase

operation begins on the selected sector(s).

Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For

each additional sector to be selected for erase, another bus cycle is issued. The bus cycle loads the next

sector-address location and the sector-erase command. The time between the end of the previous bus cycle

and the start of the next bus cycle must be less than 100

µs, otherwise the new sector location is not loaded.

A time delay of 100

µs from the rising edge of the last WE starts the sector-erase operation. If there is a falling

edge of WE within the 100

µs time delay, the timer is reset.

One to seven sector-address locations can be loaded in any sequence. The state of the delay timer can be

monitored using the sector-erase delay indicator (DQ3). If DQ3 is logic low, the time delay has not expired. See

the operation status section for a description.

Any command other than erase suspend (B0h) or sector erase (30h) written to the device during the

sector-erase operation causes the device to exit the sector-erase mode. The contents of the sector(s) selected

for erase are not valid. To complete the sector-erase operation, the sector-erase command sequence must be

repeated.

The embedded sector-erase function automatically provides needed voltage and timing to program and to verify

all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically.

Programming the memory cells prior to erase is not required.

See the operation status section for a full description. Figure 10 shows a flow chart for the typical sector-erase

device operation.