TM4SK64KPU 4194304 BY 64BIT

TM8SK64KPU 8388608 BY 64BIT

SYNCHRONOUS DYNAMIC RAM MODULES SODIMM

SMMS691A − AUGUST 1997 − REVISED NOVEMBER 1997

7

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage and ambient (unless

otherwise noted) (see Note 3)

TM4SK64KPU

PARAMETER

TEST CONDITIONS

’4SK64KPU-10

’4SK64KPU-12

UNIT

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

VOH

High-level output voltage

IOH = − 2 mA

2.4

2.4

V

VOL

Low-level output voltage

IOL = 2 mA

0.4

0.4

V

II

Input current (leakage)

0 V < VI < VDD + 0.3 V,

All other pins = 0 V to VDD

"10

"10

µA

IO

Output current (leakage)

0 V < VO < VDD +0.3 V,

Output disabled

"10

"10

µA

ICC1

Operating current

Burst length = 1,

tRC ≥ tRC MIN

CAS latency = 2

480

460

mA

ICC1

Operating current

tRC ≥ tRC MIN

IOH/IOL = 0 mA,

(see Notes 4, 5, and 6)

CAS latency = 3

540

480

mA

ICC2P

Precharge standby current in

CKE

≤ VIL MAX, tCK = 15 ns (see Note 7)

8

8

mA

ICC2PS

Precharge standby current in

power-down mode

CKE and CK

≤ VIL MAX, tCK = ∞ (see Note 8)

8

8

mA

ICC2N

Precharge standby current in

CKE

≥ VIH MIN, tCK = 15 ns (see Note 7)

160

160

mA

ICC2NS

Precharge standby current in

non-power-down mode

tCK = ∞ (see Note 8)

12

12

mA

ICC3P

Active standby current in

CKE

≤ VIL MAX, tCK = 15 ns (see Notes 4 and 7)

40

80

mA

ICC3PS

Active standby current in

power-down mode

CKE

and

CK

≤ VIL MAX, tCK = ∞

(see Notes 4 and 8)

80

80

mA

ICC3N

Active standby current in

CKE

≥ VIH MIN, tCK = 15 ns (see Notes 4 and 7)

560

520

mA

ICC3NS

Active standby current in

non-power-down mode

CKE

≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞

(see Notes 4 and 8)

160

160

mA

ICC4

Burst current

Page burst, IOH/IOL = 0 mA

All banks activated,

CAS latency = 2

1000

960

mA

ICC4

Burst current

All banks activated,

nCCD = one cycle

(see Notes 9 and 10)

CAS latency = 3

1480

1 240

mA

ICC5

Auto-refresh current

tRC ≤ tRC MIN

CAS latency = 2

1 320

1 280

mA

ICC5

Auto-refresh current

tRC ≤ tRC MIN

(see Notes 5 and 8)

CAS latency = 3

1 560

1 280

mA

ICC6

Self-refresh current

CKE

≤ VIL MAX

16

16

mA

NOTES:

3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.

4. Only one bank is activated.

5. tRC ≥ MIN

6. Control and address inputs change state twice during tRC.

7. Control and address inputs change state once every 30 ns.

8. Control and address inputs do not change state (stable).

9. Control and address inputs change once every cycle.

10. Continuous burst access, nCCD = 1 cycle