TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64BIT

TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64BIT

EXTENDEDDATAOUT DYNAMIC RAM MODULES SODIMM

SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997

8

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature

(unless otherwise noted) (continued)

TM8xJ64KPU

PARAMETER

TEST CONDITIONS†

’8xJ64KPU - 40

’8xJ64KPU -50

’8xJ64KPU - 60

UNIT

PARAMETER

TEST CONDITIONS†

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

VOH

High-level

output

IOH = − 2 mA

LVTTL

2.4

2.4

2.4

V

VOH

output

voltage

IOH = − 100 µA

LVCMOS

VDD−0.2

VDD −0.2

VDD −0.2

V

VOL

Low-level

output

IOL = 2 mA

LVTTL

0.4

0.4

0.4

V

VOL

output

voltage

IOL = 100 µA

LVCMOS

0.2

0.2

0.2

V

II

Input current

(leakage)

VDD = 3.6 V,

VI = 0 V to 3.9 V,

All others = 0 V to VDD

± 10

± 10

± 10

µA

IO

Output

current

(leakage)

VDD = 3.6 V,

VO = 0 V to VDD,

CASx high

± 10

± 10

± 10

µA

ICC1‡§

Average

read- or

write-cycle

current

VDD = 3.6 V,

Minimum cycle

644

524

444

mA

Average

VIH = 2 V (LVTTL),

After one memory cycle,

RASx and CASx high

8

8

8

mA

ICC2

Average

standby

current

VIH = VDD − 0.2 V

(LVCMOS),

’8EJ64KPU

4

4

4

mA

current

(LVCMOS),

After one memory cycle,

RASx and CASx high

’8FJ64KPU

1.2

1.2

1.2

mA

ICC3§

RASx-only

refresh,

average

refresh

curren

VDD = 3.6 V,

Minimum cycle,

RASx cycling,

CASx high

644

524

444

mA

ICC4‡¶

Average

EDO current

VDD = 3.6 V,

tHPC = MIN,

RASx low,

CASx cycling

604

484

404

mA

ICC5

Average

CBR refresh

current

VDD = 3.6 V,

Minimum cycle,

RASx low after CASx low

644

524

444

mA

ICC6#

Average

self-refresh

current

CASx < 0.2 V,

RASx < 0.2 V,

Measured after tRASS min

2.4

2.4

2.4

mA

ICC10#

Average

battery

back-up

operating

current,

CBR only

tRC = 31.25 µs,

tRAS ≤ 300 ns,

VDD − 0.2 V ≤ VIH ≤ 3.9 V,

0 V

≤ VIL ≤ 0.2 V, WE0 and OE0 = VIH,

Address and data stable

3.2

3.2

3.2

mA

† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.

‡ Measured with outputs open

§ Measured with a maximum of one address change while RASx = VIL

¶ Measured with a maximum of one address change during each EDO cycle, tHPC

# For TM8FJ64KPU only