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TM4TR64EPH Datasheet(PDF) 3 Page - Texas Instruments |
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TM4TR64EPH Datasheet(HTML) 3 Page - Texas Instruments |
3 / 22 page TM2TR64EPH, TM4TR64EPH TM2TR72EPH, TM4TR72EPH SYNCHRONOUS DYNAMIC RAM MODULES SMMS702B − JANUARY 1998 − REVISED APRIL 1998 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DUAL-IN-LINE MEMORY MODULE ( TOP VIEW ) TM4TR64EPH ( SIDE VIEW ) 1 10 11 40 84 41 PIN NOMENCLATURE A[0:10] Row-Address Inputs A[0:8] Column-Address Inputs A11/BA0 Bank-Select Zero CAS Column-Address Strobe CB[0:7] Check Bit In/Check Bit Out CKE[0:1] Clock Enable CK[0:3] System Clock DQ[0:63] Data-In / Data-Out DQMB[0:7] Data-In/Data-Out Mask Enable NC No Connect RAS Row-Address Strobe S[0:3] Chip-Select SA[0:2] Serial Presence Detect (SPD) Device Address Input SCL SPD Clock SDA SPD Address / Data VDD 3.3-V Supply VSS Ground WE Write Enable WP SPD Write-Protect TM2TR64EPH ( SIDE VIEW ) |
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