TM2TR64EPH, TM4TR64EPH

TM2TR72EPH, TM4TR72EPH

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS702B − JANUARY 1998 − REVISED APRIL 1998

9

POST OFFICE BOX 1443

−0.5 V to 4.6 V

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Voltage range on any pin (see Note 1)

− 0.5 V to 4.6 V

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Short-circuit output current

50 mA

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Power dissipation: TM2TR64EPH

8 W

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TM4TR64EPH

16 W

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TM2TR72EPH

9 W

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TM4TR72EPH

18 W

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0

°C to 70°C

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− 55

°C to 150°C

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† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

MIN

NOM

MAX

UNIT

VDD

Supply voltage

3

3.3

3.6

V

VSS

Supply voltage

0

V

VIH

High-level input voltage

2

VDD + 0.3

V

VIH-SPD High-level input voltage for the SPD device

0.7*VDD

VDD + 0.5

V

VIL

Low-level input voltage

−0.3

0.8

V

TA

Operating ambient temperature

0

70

°C

‡ The overshoot and undershoot voltage duration is less than or equal to 3 ns with no input clamp diode.

capacitance

over recommended ranges of supply voltage and ambient temperature,

PARAMETER

TMxTRxxEPH

UNIT

PARAMETER

MIN

MAX

UNIT

Ci(CK)

Input capacitance, CK input

2.5

4

pF

Ci(AC)

Input capacitance, address and control inputs: A0 − A11, RAS, CAS, WE

2.5

5

pF

Ci(CKE)

Input capacitance, CKE input

5

pF

Co

Output capacitance

4

6.5

pF

Ci(DQMBx)

Input capacitance, DQMBx input

2.5

5

pF

Ci(Sx)

Input capacitance, Sx input

2.5

5

pF

Ci/o(SDA)

Input/output capacitance, SDA input

9

pF

Ci(SPD)

Input capacitance, SA0, SA1, SA2, SCL inputs

7

pF

§ Specifications in this table represent a single SDRAM device.

NOTE 2: VDD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V.