TM2SN64EPH 2097152 BY 64BIT

TM4SN64EPH 4194304 BY 64BIT

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS706A − MARCH 1998 − REVISED APRIL 1998

9

POST OFFICE BOX 1443

serial presence detect

The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD

nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing

parameters (see Table 1 and Table 2). Only the first 128 bytes are programmed by Texas Instruments; the

remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock

(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.

See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for

further details.

SPD contents for the TMxSN64EPH devices are listed in the following tables:.

Table 1 – TM2SN64EPH

Table 2 – TM4SN64EPH

Table 1. Serial Presence Detect Data for the TM2SN64EPH

BYTE

DESCRIPTION OF FUNCTION

TM2SN64EPH-10

BYTE

NO.

DESCRIPTION OF FUNCTION

ITEM

DATA

0

Defines number of bytes written into serial memory during module manufacturing

128 bytes

80h

1

Total number of bytes of SPD memory device

256 bytes

08h

2

Fundamental memory type (FPM, EDO, SDRAM, . . .)

SDRAM

04h

3

Number of row addresses on this assembly

11

0Bh

4

Number of column addresses on this assembly

9

09h

5

Number of module rows on this assembly

1 bank

01h

6

Data width of this assembly

64 bits

40h

7

Data width continuation

00h

8

Voltage interface standard of this assembly

LVTTL

01h

9

SDRAM cycle time at maximum supported CAS latency (CL), CL = X

tCK = 10 ns

A0h

10

SDRAM access from clock at CL = X

tAC = 7.5 ns

75h

11

DIMM configuration type (non-parity, parity, error correcting code [ECC])

Non-Parity

00h

12

Refresh rate / type

15.6

µs/

self-refresh

80h

13

SDRAM width, primary DRAM

x8

08h

14

Error-checking SDRAM data width

N/A

00h

15

Minimum clock delay, back-to-back random column addresses

1 CK cycle

01h

16

Burst lengths supported

1, 2, 4, 8

0Fh

17

Number of banks on each SDRAM device

2 banks

02h

18

CAS latencies supported

2, 3

06h

19

CS latency

0

01h

20

Write latency

0

01h

21

SDRAM module attributes

Non-buffered/

Non-registered

00h

22

SDRAM device attributes: general

VDD tolerance =

(+10%),

Burst read / write,

precharge all,

auto precharge

0Eh

23

Minimum clock cycle time at CL = X − 1

tCK = 15 ns

F0h

24

Maximum data-access time from clock at CL = X − 1

tAC = 7.5 ns

75h

25

Minimum clock cycle time at CL = X − 2

N/A

00h