DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Operational amplifier circuits nearly always
employ feedback and, since feedback is the first
prerequisite for oscillation, a little caution is
appropriate. Most oscillation problems result from
driving capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 34). The value of this
capacitor is optimized empirically.
electrostatic discharge protection
The TLC2810Z incorporates an internal electrostatic discharge (ESD) protection circuit that prevents functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised,
however, when handling these devices, as exposure to ESD may result in the degradation of the device
parametric performance. The protection circuit also causes the input bias currents to be temperature dependent
and have the characteristics of a reverse-biased diode.
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2810Z
inputs and outputs are designed to withstand – 100-mA surge currents without sustaining latch-up; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes
should not by design be forward biased. Applied input and output voltages should not exceed the supply voltage
by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply
transients should be shunted by the use of decoupling capacitors (0.1
µF typical) located across the supply rails
as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
Figure 34. Compensation for Input