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1N4148WS Datasheet(PDF) 5 Page - Texas Instruments

Part # 1N4148WS
Description  TPS7A1601EVM-046
Download  9 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

1N4148WS Datasheet(HTML) 5 Page - Texas Instruments

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Board Layout
Where T
J is the junction temperature, TA is the ambient temperature, PD is the power dissipation in the
device (W), and
θ
JA is the thermal resistance from junction to ambient. All temperatures are in degrees
Celsius. The maximum silicon junction temperature, T
J, must not be allowed to exceed 150°C. The layout
design must use copper trace and plane areas effectively, as thermal sinks, in order not to allow T
J to
exceed the absolute maximum rating under all temperature conditions and voltage conditions across the
part.
The designer must consider carefully the thermal design of the PCB for optimal performance over
temperature. For this EVM, Figure 5 shows that the PCB top GND plane has six, 6-mil, thermal via
connections to the bottom-side copper GND plane to dissipate heat. The PCB is a two-layer board with
2-oz. copper on top and bottom layers. The DGN package drawing can be found at the Texas Instruments
Web site in the product folder for the TPS7A16xx LDO linear regulator.
Table 1 repeats information from the Dissipation Ratings Table of the TPS7A16xx data sheet for
comparison with the thermal resistance,
θ
JA, calculated for this EVM layout to show the wide variation in
thermal resistances for given copper areas. The High-K value is determined using a standard JEDEC
High-K (2s2p) board having dimensions of 3-inch x 3-inch with 1-oz internal power and ground planes and
2-oz copper traces on top and bottom of the board.
Table 1. Thermal Resistance,
θ
JA, and Maximum Power Dissipation
Max Dissipation without Derating
Max Dissipation without Derating
Board
Package
θ
JA
(T
A = 25°C)
(T
A = 70°C)
High-K
DGN
55.09
°C/W
1.8 mW
998 mW
TPS7A1601EVM-046
DGN
38.89
°C/W
2.57 W
1.41.W
The thermal resistance for the TPS7A1601EVM-046,
θ
JA, is the measured value for this particular layout
scheme. The maximum power dissipation is proportional to the volume of copper volume connected to the
package.
6
Board Layout
Figure 4. Top-Layer Silkscreen
5
SLVU549
– December 2011
TPS7A1601EVM-046
Submit Documentation Feedback
Copyright
© 2011, Texas Instruments Incorporated


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