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SN65HVD3082EDGKR Datasheet(PDF) 10 Page - Texas Instruments |
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SN65HVD3082EDGKR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 26 page 500 W 16 V Input D and RE Input 500 W 9 V VCC Input R Output 50 kW 50 kW 180 kW 36 kW VCC DE Input A and B Output VCC VCC Input Output 9 V 9 V 16 V 36 kW 16 V 5 W 16 V 36 kW B Input A Input VCC 16 V 16 V Input VCC Output 180 kW 36 kW SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G – AUGUST 2009 – REVISED MAY 2009 www.ti.com Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than +200 mV, and must output a Low when the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are VIT+ and VIT-and VHYS. As seen in the RECEIVER ELECTRICAL CHARACTERISTICS table, differential signals more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than +200 mV will always cause a High receiver output. When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output is High. Only when the differential input is more negative than VIT-will the receiver output transition to a Low state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT-) as well as the value of VIT+. EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E |
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