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SST28VF040A-90-4C-PH Datasheet(PDF) 3 Page - Silicon Storage Technology, Inc |
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SST28VF040A-90-4C-PH Datasheet(HTML) 3 Page - Silicon Storage Technology, Inc |
3 / 24 page Data Sheet 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A 3 ©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310 The Read operation of the SST28SF/VF040A are con- trolled by OE# and CE# at logic low. When CE # is high, the chip is deselected and only standby power will be con- sumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when CE# or OE# are high. Read-ID operation The Read-ID operation is initiated by writing a single com- mand (90H). A read of address 0000H will output the man- ufacturer’s ID (BFH). A read of address 0001H will output the device ID (04H). Any other valid command will termi- nate this operation. Data Protection In order to protect the integrity of nonvolatile data storage, the SST28SF/VF040A provide both hardware and software features to prevent inadvertent writes to the device, for example, during system power-up or power-down. Such provisions are described below. Hardware Data Protection The SST28SF/VF040A are designed with hardware fea- tures to prevent inadvertent writes. This is done in the fol- lowing ways: 1. Write Cycle Inhibit Mode: OE# low, CE#, or WE# high will inhibit the Write operation. 2. Noise/Glitch Protection: A WE# pulse width of less than 5 ns will not initiate a Write cycle. 3. VDD Power Up/Down Detection: The Write opera- tion is inhibited when VDD is less than 2.0V. 4. After power-up, the device is in the Read mode and the device is in the Software Data Protect state. Software Data Protection (SDP) The SST28SF/VF040A have software methods to further prevent inadvertent writes. In order to perform an Erase or Program operation, a two-step command sequence con- sisting of a set-up command followed by an execute com- mand avoids inadvertent erasing and programming of the device. The SST28SF/VF040A will default to Software Data Pro- tection after power up. A sequence of seven consecutive reads at specific addresses will unprotect the device The address sequence is 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The address bus is latched on the rising edge of OE# or CE#, whichever occurs first. A similar seven read sequence of 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the device. Also refer to Figures 10 and 11 for the 7 read cycle sequence Software Data Protection. The I/O pins can be in any state (i.e., high, low, or tri-state). Write Operation Status Detection The SST28SF/VF040A provide three means to detect the completion of a Write operation, in order to optimize the system Write operation. The end of a Write operation (Erase or Program) can be detected by three means: 1) monitoring the Data# Polling bit, 2) monitoring the Toggle bit, or 3) by two successive reads of the same data. These three detection mechanisms are described below. The actual completion of the nonvolatile Write is asynchro- nous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with the DQ used. In order to prevent spurious rejec- tion, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- tion is valid. Data# Polling (DQ7) The SST28SF/VF040A feature Data# Polling to indicate the Write operation status. During a Write operation, any attempt to read the last byte loaded during the byte-load cycle will receive the complement of the true data on DQ7. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 12 for Data# Polling timing waveforms. In order for Data# Polling to function correctly, the byte being polled must be erased prior to programming. Toggle Bit (DQ6) An alternative means for determining the Write operation status is by monitoring the Toggle Bit, DQ6. During a Write operation, consecutive attempts to read data from the device will result in DQ6 toggling between logic 0 (low) and logic 1 (high). When the Write cycle is completed, the tog- gling will stop. The device is then ready for the next opera- tion. See Figure 13 for Toggle Bit timing waveforms. |
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