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UCC2895-EP Datasheet(PDF) 6 Page - Texas Instruments

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Part No. UCC2895-EP
Description  BiCMOS ADVANCED PHASE-SHIFT PWM CONTROLLER
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

UCC2895-EP Datasheet(HTML) 6 Page - Texas Instruments

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F + 200
t
f(OUTA) * tf(OUTC)
t
PERIOD
F + 200
t
f(OUTB) * tf(OUTD)
t
PERIOD
or
UCC2895-EP
SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009
www.ti.com
Electrical Characteristics (continued)
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 1 μF, No load at outputs,
TA = TJ, TA = –55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Oscillator
Frequency
TJ = 25°C
473
500
527
kHz
Total variation
Line, Temperature(1)
2.5
5
%
SYNC VIH
2.05
2.1
2.32
V
SYNC VIL
1.85
1.9
1.95
V
SYNC VOH
ISYNC = –400 μA, CT = 2.6 V
4.1
4.5
5
V
SYNC VOL
ISYNC = 100 μA, CT = 0 V
0
0.5
1
V
SYNC output pulse width
SYNC load = 3.9 k
Ω and 30 pF in parallel
85
135
ns
RT voltage
2.9
3
3.1
V
CT peak voltage
2.25
2.35
2.55
V
CT valley voltage
0
0.2
0.65
V
PWM Comparator
EAOUT to RAMP/input offset voltage
RAMP = 0 V, DELAB = DELCD = REF
0.72
0.85
1.05
V
Minimum phase shift
RAMP = 0 V, EAOUT = 650 mV(2)
0
0.85
1.50
%
(OUTA to OUTC, OUTB to OUTD)
RAMP from 0 V to 2.5 V, EAOUT = 1.2 V,
RAMP to OUTC/OUTD delay
70
120
ns
DELAB = DELCD = REF(3)
RAMP bias current
RAMP < 5 V, CT < 2.2 V
–5
5
μA
RAMP sink current
RAMP = 5 V, CT < 2.6 V
12
19
mA
Current Sense
CS bias current
0 < CS< 2.5 V, 0 < ADS < 2.5 V
–4.5
20
μA
Peak current threshold
1.9
2
2.1
V
Overcurrent threshold
2.4
2.5
2.6
V
CS to output delay
CS from 0 to 2.3 V, DELAB = DELCD = REF
75
110
ns
Soft Start/Shutdown
Soft-start source current
SS/DISB = 3 V, CS = 1.9 V
–40
–35
–30
μA
Soft-start sink current
SS/DISB = 3 V, CS = 2.6 V
325
350
375
μA
Soft-start/disable comparator threshold
0.44
0.5
0.56
V
Delay Set
ADS = CS = 0 V
0.45
0.5
0.55
V
DELAB/DELCD output voltage
ADS = 0 V, CS = 2 V
1.9
2
2.1
V
Output delay
ADS = CS = 0 V(3) (4)
450
525
600
ns
ADS bias current
0 V < ADS < 2.5 V, 0 V < CS < 2.5 V
–20
20
μA
(2)
Minimum phase shift is defined as:
where:
tf(OUTA) = falling edge of OUTA signal
tf(OUTB) = falling edge of OUTB signal
tf(OUTC) = falling edge of OUTC signal
tf(OUTD) = falling edge of OUTD signal
t(PERIOD) = period of OUTA or OUTB signal
(3)
Output delay is measured between OUTA/OUTB or OUTC/OUTD. Output delay is shown in Figure 1 and Figure 2 , where:
tf(OUTA) = falling edge of OUTA signal
tr(OUTB) = rising edge of OUTB signal
(4)
Specified by design. Not production tested.
6
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