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UCC2895-EP Datasheet(PDF) 4 Page - Texas Instruments

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Part No. UCC2895-EP
Description  BiCMOS ADVANCED PHASE-SHIFT PWM CONTROLLER
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

UCC2895-EP Datasheet(HTML) 4 Page - Texas Instruments

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I
RT (A) +
3 V
R
T (W)
UCC2895-EP
SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009
www.ti.com
Table 1. PIN DESCRIPTION (continued)
NAME
DESCRIPTION
Oscillator timing resistor (see Figure 3). The oscillator in the UCC2895-EP operates by charging an external timing
capacitor, CT, with a fixed current programmed by RT. RT current is calculated as:
RT
RT can range from 40 kΩ to 120 kΩ. Soft-start charging and discharging current also are programmed by IRT.
5 V ± 1.2% voltage reference. REF supplies power to internal circuitry, and also can supply up to 5 mA to external
REF
loads. The reference is shut down during undervoltage lockout, but is operational during all other disable modes.
For best performance, bypass with a 0.1-
μF low ESR, low ESL capacitor to ground. Do not use more than 1.0 μF.
Soft start/disable. SS/DISB combines two independent functions:
Disable mode. A rapid shutdown of the chip is accomplished by any one of the following: externally forcing
SS/DISB below 0.5 V, externally forcing REF below 4 V, VDD dropping below the UVLO threshold, or an
overcurrent fault is sensed (CS = 2.5 V).
In the case of REF pulled below 4 V or an UVLO condition, SS/DISB actively is pulled to ground via an internal
MOSFET switch. If an overcurrent is sensed, SS/DISB sinks a current of 10 × IRT until SS/DISB falls below
0.5 V.
SS/DISB
Note that, if SS/DISB is externally forced below 0.5 V, the pin starts to source current equal to IRT. Also note
that the only time the part switches into the low IDD current mode is when the part is in undervoltage lockout.
Soft-start mode. After a fault or disable condition has passed and VDD is above the start threshold and/or
SS/DISB falls below 0.5 V during a soft stop, SS/DISB switches to a soft-start mode. The pin now sources
current equal to IRT. A user-selected capacitor on SS/DISB determines the soft start and soft-start time. In
addition, a resistor in parallel with the capacitor may be used, limiting the maximum voltage on SS/DISB. Note
that SS/DISB actively clamps the EAOUT voltage to approximately the SS/DISB voltage during both soft-start,
soft-stop, and disable conditions.
Synchronization (see Figure 3). SYNC is bidirectional. When used as an output, SYNC can be used as a clock,
which is the same as the chip’s internal clock. When used as an input, SYNC overrides the chip’s internal oscillator
and acts as its clock signal. This bidirectional feature allows synchronization of multiple power supplies. SYNC also
SYNC
internally discharges the CT capacitor and any filter capacitors that are present on RAMP. The internal SYNC
circuitry is level sensitive, with an input low threshold of 1.9 V and an input high threshold of 2.1 V. A resistor as
small as 3.9 k
Ω may be tied between SYNC and GND to reduce the synchronization pulse width.
VDD
Power supply. VDD must be bypassed with a minimum of a 1.0-μF low ESR, low ESL capacitor to ground.
Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply voltage
IDD < 10 mA
17
V
Supply current
30
mA
REF current
15
mA
OUT current
100
mA
Analog inputs
EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB
–0.3
REF + 0.3
V
Drive outputs
OUTA, OUTB, OUTC, OUTD
–0.3
to VCC + 0.3
N package
1
W
Power dissipation
(at TA = 25°C)
DW package
650
mW
Tstg
Storage temperature range
–65
150
°C
TJ
Junction temperature range
–55
150
°C
Lead temperature
Soldering, 10 s
300
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Currents are positive into and negative out of the specified terminal.
4
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Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): UCC2895-EP


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