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UC1875-SP Datasheet(PDF) 11 Page - Texas Instruments |
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UC1875-SP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 20 page UC1875-SP www.ti.com SLUSAQ9 – DECEMBER 2011 Delay Blocks and Output Stages In each of the output stages, transistors Q3 through Q6 form a high-speed totem-pole driver which will source or sink more than one amp peak with a total delay of approximately 30 nanoseconds. To ensure a low output level prior to turn-on, transistors Q7 through Q9 form a self-biased driver to hold Q6 on prior to the supply reaching its turn-on threshold. This circuit is operable when the chip supply is zero. Q6 is also turned on and held low with a signal from the fault logic portion of the chip. Figure 7. The delay providing the dead-time is accomplished with C1 which must discharge to VTH before the output can go high. The time is defined by the current sources, I1, which is programmed by an external resistor, RTD. The voltage on the Delay Set pins is internally regulated to 2.5 V and the range of dead time control is from 50 to 200 nanoseconds. NOTE There is no way to disable the delay circuitry, and the delay time must be programmed. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): UC1875-SP |
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