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CDCVF2505 Datasheet(PDF) 3 Page - Texas Instruments |
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CDCVF2505 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 14 page CDCVF2505 3.3V CLOCK PHASELOCK LOOP CLOCK DRIVER SCAS640E − JULY 2000 − REVISED MARCH 2005 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION 1Y[0−3] 2, 3, 5, 7 O Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25- Ω series damping resistor. CLKIN 1 I Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid signal is applied, a stabilization time (100 µs) is required for the PLL to phase lock the feedback signal to CLKIN. CLKOUT 8 O Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is made inside the chip and an external feedback loop should NOT be connected. CLKOUT can be loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs. GND 4 Power Ground VDD3.3V 6 Power 3.3-V Supply absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VDD −0.5 V to 4.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (see Notes 1 and 2) −0.5 V to VDD + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range, VO (see Notes 1 and 2) −0.5 V to VDD + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0 or VI > VDD) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < 0 or VO > VDD) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total output current, IO (VO = 0 to VDD) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 3): D package 165.5 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWR package 230.5 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg −65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.3 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 3 3.3 3.6 V High-level input voltage, VIH 0.7 VDD V Low-level input voltage, VIL 0.3 VDD V Input voltage, VI 0 VDD V High-level output current, IOH −12 mA Low-level output current, IOL 12 mA Operating free-air temperature, TA −40 85 °C |
Similar Part No. - CDCVF2505_12 |
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Similar Description - CDCVF2505_12 |
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