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Datasheet

Datasheet

BM60013FV-C

TSZ02201-0717ABH00020-1-2

© 2012 ROHM Co., Ltd. All rights reserved.

29.May.2012 Rev.002

www.rohm.com

TSZ22111・15・001

●

Operational Notes

(1) Absolute maximum ratings

An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc.,

can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open

circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection

devices, such as fuses.

Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power

supply lines. An external direction diode can be added.

(3) Power supply Lines

Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply

line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply

terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic

capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures.

(4) GND Potential

The potential of GND1 pin must be minimum potential in all operating conditions. (Input side ; 11pin to 20pin)

The potential of VEE2 pin must be minimum potential in all operating conditions. (Output side ; 1pin to 10pin)

(5) Thermal design

Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.

(6) Inter-pin shorts and mounting errors

When attaching to a printed circuit board, pay close attention to the direction of the IC and displacement. Improper

attachment may lead to destruction of the IC. There is also possibility of destruction from short circuits which can be

caused by foreign matter entering between outputs or an output and the power supply or GND.

(7) Operation in a strong electric field

Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to

malfunction.

(8) Inspection of the application board

During inspection of the application board, if a capacitor is connected to a pin with low impedance there is a possibility

that it could cause stress to the IC, therefore an electrical discharge should be performed after each process. Also, as a

measure again electrostatic discharge, it should be earthed during the assembly process and special care should be

taken during transport or storage. Furthermore, when connecting to the jig during the inspection process, the power

supply should first be turned off and then removed before the inspection.

(9) Input terminal of IC

Between each element there is a P+ isolation for element partition and a P substrate. This P layer and each element’s

N layer make up the P-N junction, and various parasitic elements are made up.

For example, when the resistance and transistor are connected to the terminal as shown in figure 61,

○

When GND＞(Terminal A) at the resistance and GND＞(Terminal B) at the transistor (NPN), the P-N

junction operates as a parasitic diode.

○

Also, when GND＞(Terminal B) at the transistor (NPN), The parasitic NPN transistor operates with the

N layers of other elements close to the aforementioned parasitic diode.

Because of the IC’s structure, the creation of parasitic elements is inevitable from the electrical potential relationship. The

operation of parasitic elements causes interference in circuit operation, and can lead to malfunction and destruction. Therefore,

be careful not to use it in a way which causes the parasitic elements to operate, such as by applying voltage that is lower than

the GND (P substrate) to the input terminal.

(10) Ground Wiring Patterns

When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,

placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage

variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change

the GND wiring pattern potential of any external components, either.

Status of this document

The Japanese version of this document is formal specification. A customer may use this translation version only for a

reference to help reading the formal version.

If there are any differences in translation version of this document formal version takes priority

Figure 61. Pattern Diagram of Parasitic Element

Resistor

Transistor(NPN)

N

N

N

P

+

P

+

P

P substrate

GND

Parasitic

element

Terminal A

N

N

P

+

P

+

P

P substrate

GND

Parasitic

element

Terminal B

C

B

E

N

GND

Terminal A

Parasitic

element

Terminal B

Other adjacent elements

E

B

C

GND

Parasitic

element