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SST89C54-33-AC-NI Datasheet(PDF) 1 Page - Silicon Storage Technology, Inc |
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SST89C54-33-AC-NI Datasheet(HTML) 1 Page - Silicon Storage Technology, Inc |
1 / 50 page 1 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications © 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. FlashFlex, In-Application Programming, IAP and SoftLock are 344-2 8/00 trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FEATURES: • Multi-Purpose 8-bit 8051 Family Compatible Microcontroller Unit (MCU) with Embedded SuperFlash Memory • Fully Software and Development Toolset Compatible as well as Pin-For-Pin Package Compatible with Standard 8xC5x Microcontrollers • 256 Bytes Register/Data RAM • 20/36 KByte Embedded High Performance Flexible SuperFlash EEPROM – One 16/32 KByte block (128-Byte sector size) – One 4 KByte block (64-Byte sector size) – Individual Block Security Lock with Softlock™ feature – 87C5x Programmer Compatible – Concurrent Operation during In-Application Programming™(IAP™) – Memory Re-Mapping for Interrupt Support during IAP • Support External Address Range up to 64 KByte of Program and Data Memory • High Current Drive on Port 1 (5, 6, 7) pins • Three 16-bit Timer/Counter • Programmable Serial Port (UART) • Six Interrupt Sources at 2 Priority Levels • Selectable Watchdog Timer (WDT) • Four 8-bit I/O Ports (32 I/O Pins) • TTL- and CMOS-Compatible Logic Levels • Extended Power-Saving Modes – Idle Mode – Power Down Mode with External Interrupt Wake-up – Standby (Stop Clock) Mode • High Speed Operation at 5 Volts (0 to 33MHz) • Low Voltage (2.7V) Operation (0 to 12MHz) • PDIP-40, PLCC-44 and TQFP-44 Packages • Temperature Ranges: – Commercial (0°C to +70°C) – Industrial (-40°C to +85°C) PRODUCT DESCRIPTION SST89C54 and SST89C58 are members of the FlashFlex51 family of 8-bit microcontrollers. The FlashFlex51 family is a family of embedded microcontroller products designed and manufactured on the state-of-the-art SuperFlash CMOS semiconductor process technology. As a member of the FlashFlex51 controller family, the SST89C54/58 uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with standard 8xC5x microcontroller devices. SST89C54/58 comes with 20/36 KByte of integrated on-chip flash EEPROM program memory using the patented and proprietary Silicon Storage Technology, Inc. (SST) CMOS SuperFlash EEPROM technology with the SST field enhancing tunneling injector split-gate memory cells. The SuperFlash memory is partitioned into 2 independent program memory blocks. The primary SuperFlash Block 0 occu- pies 16/32 KByte of internal program memory space and the secondary SuperFlash Block 1 occupies 4 KByte of SST89C54/58’s internal program memory space. The 4 KByte secondary SuperFlash block can be mapped to the highest or lowest location of the 64 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory. The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and firmware for SST89C54/58 devices. During the power-on reset, the SST89C54/58 can be configured as a master for source code storage or as a slave to an external host for In-Application Programming (IAP) operation. SST89C54/58 is de- signed to be programmed “In-System” and “In-Applica- tion” on the printed circuit board for maximum flexibility. The device is pre-programmed with a sample bootstrap loader in the memory (see Note 1), demonstrating the initial user program code loading or subsequent user code updating via the “IAP” operation. In addition to 20/36 KByte of SuperFlash EEPROM program memory on-chip, the SST89C54/58 can ad- dress up to 64 KByte of program memory external to the chip. The SST89C54/58 have 256 x 8 bits of on-chip RAM. Up to 64 KByte of external data memory (RAM) can be addressed. The highly reliable, patented SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs, when compared with other approaches. These advantages translate into significant cost and reliability benefits for our customers. Note 1: The sample bootstrap loader is for the user’s reference and convenience only. SST does not guarantee the functionality or the usefulness of the sample bootstrap loader. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code. |
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