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TPS84250RKGR Datasheet(PDF) 14 Page - Texas Instruments |
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TPS84250RKGR Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 29 page  INH/UVLO VIN RUVLO1 RUVLO2 AGND V IN ( ) ( ) - = W æ ö - + ´ ç ÷ ç ÷ è ø UVLO2 ON 3 UVLO1 1.25 R k V 1.25 0.9 10 R ( ) ( ) - - = W ´ ON OFF UVLO1 3 V V R k 2.9 10 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com Undervoltage Lockout (UVLO) Threshold At turn-on, the VON UVLO threshold determines the input voltage level where the device begins power conversion. During the power-down sequence, the VOFF UVLO threshold determines the input voltage where power conversion ceases. The turn-on and turn-off thresholds are set by two resistors, RUVLO1 and RUVLO2 as shown in Figure 26. The VON UVLO threshold must be set to at least (VOUT + 3 V) or 7 V whichever is greater to insure proper start- up and reduce current surges on the host input supply as the voltage rises. If possible, it is recommended to set the UVLO threshold to appproximantely 80 to 85% of the minimum expected input voltage. Use Equation 2 and Equation 3 to calculate the values of RUVLO1 and RUVLO2. VON is the voltage threshold during power-up when the input voltage is rising. VOFF is the voltage threshold during power-down when the input voltage is decreasing. VOFF should be selected to be at least 500mV less than VON. Table 4 lists standard resistor values for RUVLO1 and RUVLO2 for adjusting the VON UVLO threshold for several input voltages. (2) (3) Figure 26. Adjustable VIN UVLO Table 4. Standard Resistor Values to set VON UVLO Threshold VON THRESHOLD (V) 6.5 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 RUVLO1 (kΩ) 174 174 174 174 174 174 174 174 174 RUVLO2 (kΩ) 40.2 24.3 15.8 11.5 9.09 7.50 6.34 5.62 4.99 Power Good (PWRGD) The PWRGD pin is an open drain output. Once the output voltage is between 94% and 106% of the set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 k Ω and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the output voltage is lower than 91% or greater than 109% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V. 14 Copyright © 2012, Texas Instruments Incorporated |
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