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SST39SF512-70-4C-PH Datasheet(PDF) 3 Page - Silicon Storage Technology, Inc |
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SST39SF512-70-4C-PH Datasheet(HTML) 3 Page - Silicon Storage Technology, Inc |
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3 / 22 page  Data Sheet 512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 3 ©2001 Silicon Storage Technology, Inc. S71149-03-000 4/01 394 Toggle Bit (DQ6) During the internal Program or Erase operation, any con- secutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. The Toggle Bit will begin with “1”. When the internal Program or Erase opera- tion is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program oper- ation. For Sector or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. Data Protection The SST39SF512/010 provide both hardware and soft- ware features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The write operation is inhibited when VDD is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. Software Data Protection (SDP) The SST39SF512/010 provide the JEDEC approved Soft- ware Data Protection scheme for all data alteration opera- tions, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Pro- gram operation, providing optimal protection from inadvert- ent write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST39SF512 device is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid com- mands will abort the device to read mode, within TRC. Product Identification The product identification mode identifies the device as the SST39SF512 and SST39SF010 and manufacturer as SST. This mode may be accessed by software operations. Users may use the software product identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software oper- ation, Figure 11 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accom- plished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing wave- form and Figure 17 for a flowchart. TABLE 1: PRODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H BFH Device ID SST39LF/VF512 0001H B4H SST39LF/VF010 0001H B5H T1.1 394 |
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