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TPS65300QRHFRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS65300QRHFRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 36 page  1 2 3 4 5 6 7 19 18 17 16 15 14 13 8 9 10 11 12 24 23 22 21 20 BOOT VIN IGN_EN BOOT_LDO NC RT/CLK EN DELAY RHF Package (Top View) SS 3.3VDRIVE 3.3VSENSE 1,2VDRIVE 1.2VSENSE VSENSE P0057-02 1 2 3 4 5 6 7 8 9 11 10 12 24 23 22 21 20 19 18 17 16 14 15 13 PWP Package (Top View) P0110-03 PH VIN_D BOOT IGN_ST VIN IGN_EN BOOT_LDO NC RT/CLK EN 5V GND PGND nRST VREG DELAY SS 3.3VDRIVE 3.3VSENSE 1.2VDRIVE 1.2VSENSE VSENSE COMP NC TPS65300-Q1 SLVSBB6B – MARCH 2012 – REVISED APRIL 2012 www.ti.com DEVICE INFORMATION Table 1. Pin Descriptions PIN NUMBER I/O DESCRIPTION NAME PWP RHF PH 1 23 O Source of internal switching FET Drain input for internal high side MOSFET. Pin 2 and pin 4 must be VIN_D 2 24 I connected together externally. External bootstrap capacitor connected to PH (pin 1) to drive gate of BOOT 3 1 O internal switching FET Unregulated input voltage supply. Pin 2 and pin 4 must be connected VIN 4 2 I together externally. Ignition input (high-voltage tolerant) internally pulls to ground. Must be IGN_EN 5 3 I externally pulled up to enable BOOT_LDO 6 4 O External capacitor connected to ground for stability of internal regulator NC 7 5 – Connect to ground External resistor connected ground to program the internal oscillator. RT/CLK 8 6 I/O Alternative option is to feed an external clock to provide reference for switching frequency. A high logic-level input signal to enable and low signal to disable device. EN 9 7 I Internally pulled down to ground 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS65300-Q1 |
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