Electronic Components Datasheet Search |
|
SST49LF002A-33-4C-NH Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc |
|
SST49LF002A-33-4C-NH Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc |
5 / 36 page Advance Information 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A 5 ©2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 Abort Mechanism If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated and the device will wait for the ABORT command. The host must drive the FWH[3:0] with ‘1111b’ (ABORT command) to return the device to ready mode. If abort occurs during the internal write cycle, the data may be incorrectly programmed or erased. It is required to wait for the Write operation to com- plete prior to initiation of the abort command. It is recom- mended to check the Write status with Data# Polling (DQ7) or Toggle Bit (DQ6) pins. One other option is to wait for the fixed write time to expire. Response To Invalid Fields During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: Address out of range: The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be decoded by SST49LF00xA. Address A22 has the special function of directing reads and writes to the flash core (A22=1) or to the register space (A22=0). The SST49LF003A features are equivalent to the SST49LF004A with 128 KByte less memory. For the SST49LF003A, operations beyond the 3-Mbit bound- ary (below 20000H) are not valid (see Device Memory Map). Invalid address range locations will read as 00H. Invalid IMSIZE field: If the FWH receives an invalid size field during a Read or Write operation, the device will reset and no operation will be attempted. The SST49LF00xA will not generate any kind of response in this situation. Invalid- size fields for a Read/Write cycle are anything but 0000b. Once valid START, IDSEL, and IMSIZE fields are received, the SST49LF00xA always will respond to subsequent inputs as if they were valid. As long as the states of device FWH[3:0] and FWH4 are known, the response of the SST49LF00xA to signals received during the FWH cycle should be predictable. The SST49LF00xA will make no attempt to check the validity of incoming flash operation commands. Device Memory Hardware Write Protection The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory in the SST49LF00xA. The TBL# pin is used to write protect 16 boot sectors (64 KByte) at the highest flash memory address range for the SST49LF003A/ 004A/008A and 4 boot sectors (16 KByte) for SST49LF002A. WP# pin write protects the remaining sectors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors. When TBL# pin is held high, write protection of the top boot sectors is then determined by the Boot Block Locking register. The WP# pin serves the same function for the remaining sectors of the device memory. The TBL# and WP# pins write protec- tion functions operate independently of one another. Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase operation could cause unpredictable results. TBL# and WP# pins cannot be left unconnected. TBL# is internally ORed with the top Boot Block Locking register. When TBL# is low, the top Boot Block is hard- ware write protected regardless of the state of the Write- Lock bit for the Boot Block Locking register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional effect, even though the register may indicate that the block is no longer locked. WP# is internally ORed with the Block Locking register. When WP# is low, the blocks are hardware write pro- tected regardless of the state of the Write-Lock bit for the corresponding Block Locking registers. Clearing the Write-Protect bit in any register when WP# is low will have no functional effect, even though the register may indicate that the block is no longer locked. Reset A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, FWH[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase operation. See Table 18, Reset Timing Parameters for more information. A device reset during an active Program or Erase will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete Erase or Program operation. |
Similar Part No. - SST49LF002A-33-4C-NH |
|
Similar Description - SST49LF002A-33-4C-NH |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |